本文關(guān)鍵詞：體系結(jié)構(gòu)級Cache功耗優(yōu)化技術(shù)研究　出處：《浙江大學(xué)》2013年博士論文　論文類型：學(xué)位論文

  更多相關(guān)文章： 高速緩存 體系結(jié)構(gòu) 功耗優(yōu)化 指令高速緩存 數(shù)據(jù)高速緩存 可重構(gòu)高速緩存

【摘要】：隨著集成電路制造工藝的進步和微處理器性能的提高,微處理器功耗問題日益嚴重,成為制約微處理器發(fā)展的主要瓶頸。片上高速緩存(Cache)功耗作為微處理器功耗的重要組成部分,降低Cache功耗成為控制微處理器功耗的主要目標。由于底層功耗優(yōu)化手段受工藝和材料物理特性的制約已經(jīng)很難滿足Cache的功耗約束,因此需要從更高層次對Cache功耗進行優(yōu)化。本文從Cache功耗的組成、訪問特性、功耗性能平衡等多個角度出發(fā),提出了多項體系結(jié)構(gòu)級Cache功耗優(yōu)化方法。主要研究工作和創(chuàng)新點包括： 低功耗指令Cache研究。針對指令Cache行間訪問偏移范圍存在明顯局部性特征,提出了一種將Cache當(dāng)前訪問行及其若干緊鄰行鏈接訪問的低功耗指令緩存訪問方法。該方法能夠在發(fā)生相對跳轉(zhuǎn)時依托于相鄰行之間的訪問鏈接信息,精確獲得跳轉(zhuǎn)目標行的路訪問信息,從而減少對Cache標志和數(shù)據(jù)存儲器的訪問,達到降低指令Cache動態(tài)功耗的目的。在Cache行發(fā)生替換時,僅需檢測并清除相鄰緩存行與被替換行的鏈接信息,以很小的硬件代價實現(xiàn)鏈接信息的正確性。 低功耗數(shù)據(jù)Cache研究。針對數(shù)據(jù)Cache與存儲加載隊列并行訪問的功耗問題和串行訪問的性能問題,提出了一種基于存儲加載隊列預(yù)測訪問過濾無效數(shù)據(jù)Cache訪問的低功耗方法。利用內(nèi)存相關(guān)性的可預(yù)測特征,通過記錄加載指令與存儲加載隊列中存在內(nèi)存相關(guān)性的指令集合,預(yù)測后續(xù)僅需訪問存儲加載隊列的加載指令,直接從存儲加載隊列前饋數(shù)據(jù)通路獲取加載結(jié)果,關(guān)閉數(shù)據(jù)Cache的訪問。 Cache可重構(gòu)算法研究。針對可重構(gòu)Cache中重構(gòu)搜索的開銷問題,提出了一種基于函數(shù)轉(zhuǎn)移開啟Cache重新配置的可重構(gòu)預(yù)測算法。利用函數(shù)轉(zhuǎn)移獲取新程序段的特性,以函數(shù)為單位動態(tài)監(jiān)測Cache缺失率變化,通過函數(shù)歷史最優(yōu)Cache配置參數(shù)預(yù)測后續(xù)函數(shù)的Cache重構(gòu)配置信息,減少重構(gòu)過程對Cache設(shè)計空間的搜索；進一步,通過區(qū)分重構(gòu)前后的緩存行,使重構(gòu)后Cache能夠繼續(xù)使用重構(gòu)前的緩存數(shù)據(jù),降低了Cache初始化的延時和功耗。 Cache無效訪問研究。針對分支行為預(yù)測錯誤導(dǎo)致指令Cache的無效訪問,提出了一種基于零延時分支預(yù)測的指令Cache低功耗方法,利用分支預(yù)測的行為信息參與后續(xù)分支行為預(yù)測,消除深流水、超標量處理器中由于分支代價高導(dǎo)致分支歷史重名問題,提高分支行為的預(yù)測準確率,減少指令Cache無效訪問功耗。 本文提出的多項體系結(jié)構(gòu)級Cache功耗優(yōu)化方法能夠在不影響性能的前提下,有效降低Cache功耗,改善微處理器的性能功耗比。
[Abstract]:With the development of integrated circuit and microprocessor performance improvement, microprocessor power consumption is becoming increasingly serious, has become the main bottleneck for the development of microprocessor. The on-chip cache (Cache) power consumption as an important part of microprocessor power consumption, lower power consumption has become the main target of Cache microprocessor to control power consumption. Due to the restriction of power by means of optimization process and bottom the characteristics of composite materials has been difficult to meet the power constraints of Cache, therefore need to optimize power consumption of Cache from a higher level. This article from the composition of Cache power, access characteristics, multi angle performance power balance and so on, put forward a number of system structure Cache power optimization method. The main research work and innovation include:
Low power instruction Cache research. According to the instruction Cache access interline offset range has obvious local characteristics, proposed a low power instruction cache Cache for the current access and several adjacent line link access method. This method can in the relative jump between adjacent rows based on the access link information, precise jump target the way of access to information, thus reducing the Cache signs and data access, to reduce power consumption of instruction Cache dynamic purpose. For Cache substitution, only need to detect and remove adjacent cache line is replaced with the link information, realize the correct link information with little hardware overhead.
Study on Cache data with low power consumption. According to the performance data of Cache and storage load queue parallel access power and serial access, we proposed a prediction filter invalid data Cache access storage load queue based on low power consumption method. The use of memory between predictable characteristics, through the memory load instruction and storage load correlation record the queue in the instruction set, predict the following only access storage loading queue load instruction, obtain loading results directly from the storage load queue feedforward data path, close the Cache data access.
Cache study of reconstruction algorithm. The reconstruction overhead problem in Cache search, proposed a transfer function of open Cache reconfiguration of reconfigurable prediction algorithm based on transfer function. Based on the characteristics of acquiring new program segments, to function as a unit of dynamic monitoring of Cache deletion rate, prediction of Cache reconstruction of configuration information through the following function the historical function of optimal Cache configuration parameters, reduce the search space of the Cache reconstruction process design; further, by distinguishing the cache line before and after the reconstruction, the reconstructed Cache can continue to use the number of cache reconstruction before according to reduced Cache initialization, delay and power consumption.
Study on access invalid Cache. According to the error caused the invalid access instruction Cache branch behavior prediction, proposes a method of low power instruction Cache zero delay branch prediction based on the behavior of information involved in the subsequent branch branch prediction behavior, the elimination of deep water, the amount of processing in the branch history due to exceed the standard problem due to the high cost of the same branch, improve the behavior of branch prediction accuracy, reduce instruction Cache invalid access power.
In this paper, a number of architecture level Cache power optimization methods can effectively reduce Cache power consumption and improve the performance and power consumption of microprocessors without affecting the performance.

【學(xué)位授予單位】：浙江大學(xué)
【學(xué)位級別】：博士
【學(xué)位授予年份】：2013
【分類號】：TP332

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本文編號：1379274