本文關(guān)鍵詞：基于PowerPCAltiVec模擬器的研究與實現(xiàn)　出處：《廣西工學院》2012年碩士論文　論文類型：學位論文

  更多相關(guān)文章： 虛擬原型 AltiVec技術(shù) 可變長度指令編碼 底層虛擬機

【摘要】：在嵌入式系統(tǒng)設(shè)計中，工程師們通常采用模型驅(qū)動工程（MDE）的方法來建立軟、硬件高層次模型。而快速虛擬原型平臺正是可以在高層次抽象下模擬系統(tǒng)的工具軟件，而不僅僅是泛函算法仿真�？焖偬摂M原型平臺可在形式化描述中得到精細化的模擬器模型，而且可運行并測試完整的嵌入式應(yīng)用軟件。快速虛擬原型平臺已經(jīng)成為了嵌入式片上系統(tǒng)軟、硬件協(xié)同設(shè)計的關(guān)鍵所在。 嵌入式系統(tǒng)隨著硬件性能的增強而不斷發(fā)展，而現(xiàn)有虛擬原型中的單一模擬器在模擬功能及效率上不能夠滿足軟、硬件協(xié)同開發(fā)的需求。因此在嵌入式軟件系統(tǒng)領(lǐng)域研究新的模擬及模擬優(yōu)化技術(shù)，在快速虛擬原型架構(gòu)下開發(fā)高效高可信的模擬器有著重要的意義。過去十幾年以來，科研人員主要針對虛擬原型中32位及64位嵌入式處理器的模擬器展開了大量研究，而很少關(guān)注128位協(xié)處理器模擬器。事實上，協(xié)處理器的性能直接決定了嵌入式系統(tǒng)在某些應(yīng)用方面的性能，，如多媒體、矢量繪圖、通信等應(yīng)用。隨著128位協(xié)處理器多媒體應(yīng)用等的繼續(xù)增長，會給處理器虛擬原型研究領(lǐng)域帶來更多的挑戰(zhàn)。近似定時模擬技術(shù)（AT）、編譯器優(yōu)化技術(shù)（LLVM）、可變長度指令編碼技術(shù)（VLE）等都是該領(lǐng)域存在的難題。因此本研究以挑戰(zhàn)嵌入式系統(tǒng)設(shè)計和仿真的新方法為切入點，結(jié)合先進的系統(tǒng)建模和系統(tǒng)驗證技術(shù)，在SimSoC虛擬原型的基礎(chǔ)上研究了基于PowerPCAltiVec128位指令集的近似定時模擬技術(shù)、底層虛擬機（LLVM）動態(tài)編譯優(yōu)化技術(shù)和基于PowerPC模擬器的VLE可變長度指令編碼技術(shù)以及模擬器仿真和驗證技術(shù)，最終實現(xiàn)了高效高可信的基于SimSoC快速虛擬原型平臺的PowerPCAltiVec嵌入式片上系統(tǒng)模擬器。 本論文的主要工作有：第一，提出了構(gòu)建PowerPC AltiVec128位嵌入式協(xié)處理器技術(shù)的GCC交叉編譯器工具鏈的新方法。該工具鏈具有可移植性高、編譯速度快、完整支持PowerPCAltiVec指令集及內(nèi)建AltiVec系統(tǒng)函數(shù)等特點。第二，為了研究分析虛擬原型的計算和譯碼效率，分別采用了解釋型編譯、動態(tài)編譯、細化動態(tài)編譯技術(shù)來設(shè)計和實現(xiàn)PowerPC AltiVec指令集模擬器。研究了先進的用于優(yōu)化模擬器執(zhí)行效率的基于底層虛擬機（LLVM）動態(tài)編譯技術(shù)。將可變長度指令編碼技術(shù)應(yīng)用于PowerPC AltiVec128位指令集模擬器，為其提供更好的編碼密度，提高單位存儲芯片空間的利用率。第三，在仿真實驗中比較了在不同編譯模式下PowerPC AltiVec指令集模擬器執(zhí)行應(yīng)用程序的效率和可信度。最后，通過單元測試、集成測試和系統(tǒng)測試對PowerPC AltiVec指令集模擬器進行完整的跟蹤及測試以達到其可驗證性。
[Abstract]:In embedded system design, engineers usually use model-driven engineering (MDE) to build software. The hardware high-level model. And the rapid virtual prototype platform is the tool software which can simulate the system under the high-level abstraction. It is not just functional algorithm simulation. The rapid virtual prototype platform can obtain a refined simulator model in formal description. The rapid virtual prototyping platform has become the key of the software and hardware collaborative design of embedded system. With the development of hardware performance, the single simulator in the existing virtual prototype can not meet the simulation function and efficiency. Therefore, new simulation and simulation optimization techniques are studied in the field of embedded software system. It is of great significance to develop an efficient and trusted simulator in the framework of rapid virtual prototyping. Over the past more than ten years. Researchers mainly focus on the virtual prototype of 32-bit and 64-bit embedded processor emulators, but pay little attention to 128-bit coprocessor emulators. The performance of coprocessor directly determines the performance of embedded system in some applications, such as multimedia, vector drawing, communication and so on. It will bring more challenges to the field of processor virtual prototyping. Approximate timing simulation technology, compiler optimization technology LLVM). Variable length instruction coding (VLEE) is a difficult problem in this field. Therefore, this research focuses on the challenge of new methods of embedded system design and simulation. Combined with advanced system modeling and system verification technology, the approximate timing simulation technology based on PowerPCAltiVec128 bit instruction set is studied on the basis of SimSoC virtual prototype. The dynamic compilation and optimization technology of the underlying virtual machine, the VLE variable length instruction coding technology based on PowerPC simulator, and the simulator simulation and verification technology. Finally, an efficient and trusted PowerPCAltiVec embedded system simulator based on SimSoC rapid virtual prototype platform is implemented. The main work of this paper is as follows: first. A new method of constructing GCC cross-compiler toolchain based on PowerPC AltiVec128 bit embedded coprocessor technology is presented, which has high portability and high compilation speed. Fully support the PowerPCAltiVec instruction set and built-in AltiVec system functions. Second, in order to study the virtual prototype of computing and decoding efficiency. Interpretive compilation and dynamic compilation are used respectively. Design and implementation of PowerPC AltiVec instruction set simulator based on dynamic compilation technology. Dynamic compiling technique. The variable length instruction coding technique is applied to PowerPC AltiVec128 bit instruction set simulator. To provide a better coding density, improve the utilization of unit memory chip space. Third. In the simulation experiment, the efficiency and reliability of the PowerPC AltiVec instruction set simulator to execute the application program in different compilation modes are compared. Finally, the unit test is passed. PowerPC AltiVec instruction set simulator is tracked and tested by integrated test and system test to achieve its verifiability.
【學位授予單位】：廣西工學院
【學位級別】：碩士
【學位授予年份】：2012
【分類號】：TP368.1

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