本文關(guān)鍵詞： EtherCAT網(wǎng)絡(luò) 數(shù)據(jù)采集系統(tǒng) 同步性控制 PCIe FPGA　出處：《大連理工大學(xué)》2015年碩士論文　論文類型：學(xué)位論文

【摘要】：在海洋工程模型的研究試驗中,測量系統(tǒng)受自身的封閉性、獨(dú)立性等條件限制,各類測量儀器單獨(dú)運(yùn)行,獨(dú)立采集、存儲及上傳實驗數(shù)據(jù),從而影響到了整個測試系統(tǒng)的實時同步控制、觀測與處理。為了提高數(shù)據(jù)傳輸?shù)膶崟r性和同步性,將EtherCAT實時以太網(wǎng)技術(shù)引入數(shù)據(jù)采集系統(tǒng),將各個獨(dú)立的從站統(tǒng)一連接,為高速實時的現(xiàn)代化數(shù)據(jù)采集系統(tǒng)提供了理想平臺。本文介紹了網(wǎng)絡(luò)化數(shù)據(jù)采集系統(tǒng)的研究現(xiàn)狀和發(fā)展前景,針對沒有EtherCAT網(wǎng)絡(luò)接口的數(shù)據(jù)采集系統(tǒng)從站類型,設(shè)計了一款基于PCIe總線的從站通信卡。本設(shè)計實現(xiàn)了一種新的EtherCAT從站設(shè)計形式,通過這款具有EtherCAT網(wǎng)絡(luò)從站功能的PCIe通信卡,將需要計算機(jī)獨(dú)立管理的數(shù)據(jù)采集系統(tǒng)從站成功接入到EtherCAT網(wǎng)絡(luò)。該方案改變并拓寬了EtherCAT從站實現(xiàn)形式,提高了數(shù)據(jù)采集系統(tǒng)從站的整體性能,為研究和應(yīng)用EtherCAT技術(shù)提供了一種新的途徑。該通信卡包括三大核心芯片：FPGA.STM32和ET1100。從站設(shè)備將采集的數(shù)據(jù)通過PCIe,總線傳輸?shù)紽PGA, FPGA將數(shù)據(jù)轉(zhuǎn)化后通過SPI總線傳送到STM32單片機(jī),單片機(jī)將數(shù)據(jù)進(jìn)行編碼、映射后借助于從站控制器芯片ET1100將數(shù)據(jù)成功傳輸至EtherCAT網(wǎng)絡(luò)。本文將從系統(tǒng)從站的整體設(shè)計方案、系統(tǒng)從站硬件的的設(shè)計及實現(xiàn)、系統(tǒng)從站軟件的設(shè)計與實現(xiàn)等幾個方面展開論述。首先詳細(xì)介紹了系統(tǒng)從站硬件電路的設(shè)計,包括PCIe接口設(shè)計、FPGA器件選型及電路設(shè)計、EtherCAT通信模塊電路設(shè)計和電源電路設(shè)計,然后介紹EtherCAT網(wǎng)絡(luò)從站軟件程序設(shè)計包括STM32程序設(shè)計、FPGA程序設(shè)計以及系統(tǒng)從站驅(qū)動程序的開發(fā),最后對整個EtherCAT網(wǎng)絡(luò)化數(shù)據(jù)采集系統(tǒng)從站進(jìn)行調(diào)試和性能測試。首先在QuartusⅡ 11.0軟件開發(fā)環(huán)境下,利用Signal TapII在線邏輯分析儀測試了PCIe總線數(shù)據(jù)傳輸時序和FPGA內(nèi)部數(shù)據(jù)傳輸時序,然后利用倍福公司的TwinCAT軟件進(jìn)行網(wǎng)卡整體傳輸性能測試,最后利用實驗室自主研發(fā)的系統(tǒng)主站軟件進(jìn)行從站網(wǎng)卡的數(shù)據(jù)傳輸性能測試。實驗表明,基于PCIe,總線的EtherCAT網(wǎng)絡(luò)化數(shù)據(jù)采集系統(tǒng)從站性能良好,滿足了數(shù)據(jù)傳輸?shù)膶崟r性、同步性、準(zhǔn)確性的要求。
[Abstract]:In the research and test of ocean engineering model, the measurement system is restricted by its own closure and independence, and all kinds of measuring instruments run alone, collect, store and upload the experimental data independently. In order to improve the real-time and synchronicity of data transmission, EtherCAT real-time Ethernet technology is introduced into the data acquisition system, and each independent slave station is connected uniformly, so that the real-time synchronization control, observation and processing of the whole test system are affected, and in order to improve the real-time and synchronization of data transmission, the EtherCAT real-time Ethernet technology is introduced into the data acquisition system. It provides an ideal platform for modern data acquisition system with high speed and real time. This paper introduces the research status and development prospect of networked data acquisition system, aiming at the slave station type of data acquisition system without EtherCAT network interface. A slave station communication card based on PCIe bus is designed. This design realizes a new EtherCAT slave station design form, through this PCIe communication card which has the function of EtherCAT network slave station, The data acquisition system which needs computer independent management is successfully connected to the EtherCAT network. The scheme changes and widens the realization form of the EtherCAT slave station and improves the overall performance of the slave station of the data acquisition system. This communication card includes three core chips: FPGA.STM32 and ET1100.The data collected by slave equipment is transmitted to FPGA via PCI, and transferred to FPGA by FPGA, and then transferred to STM32 microcontroller by FPGA bus, and the communication card is composed of three core chips: FPGA.STM32 and ET1100. The MCU encodes the data and transmits the data successfully to the EtherCAT network by means of the slave controller chip ET1100. In this paper, the whole design scheme of the slave station and the hardware design and implementation of the slave station are introduced. The system is discussed from several aspects, such as the design and realization of the station software. Firstly, the hardware circuit design of the system slave station is introduced in detail, including the PCIe interface design, FPGA device selection and circuit design, and the circuit design of EtherCAT communication module and power supply circuit. Then the software design of EtherCAT network slave station includes STM32 program design and the development of system slave station driver. Finally, the slave station of the whole EtherCAT network data acquisition system is debugged and its performance is tested. Firstly, in the Quartus 鈪，

本文編號：1517226