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時差定位算法及授時信息傳輸實現(xiàn)研究

發(fā)布時間:2019-01-14 16:46
【摘要】:隨著全球電子信息技術(shù)的發(fā)展越來越迅猛, GPS(Global Position Systems)技術(shù)日益成熟,為無源時差估計提供了很好的實現(xiàn)平臺。由于無源時差定位技術(shù)在許多性能上明顯優(yōu)于有源定位技術(shù),所以無源時差定位技術(shù)受到越來越高的重視,成為國內(nèi)外眾多學(xué)者重點研究對象。 本文圍繞著如何實現(xiàn)無源時差定位系統(tǒng)展開了深入研究。首先對無源時差估計和無源時差定位算法進行了理論介紹,針對不同仿真環(huán)境進行了大量的Matlab仿真研究,并通過仿真結(jié)果,從均值及均方誤差對算法進行了比較分析,最后討論聯(lián)合時延估計算法和聯(lián)合時差定位算法。Matlab仿真結(jié)果表明,聯(lián)合時延估計算法加快了算法收斂速度,并大大減少了EDTE的濾波器階數(shù),有利于工程實現(xiàn);聯(lián)合時差定位算法提高了定位精度,并且在即使TDOA誤差較大時,也可以很準(zhǔn)確估算出目標(biāo)位置,同時避免了算法的不收斂性。 然后本文對如何實現(xiàn)無源時差定位系統(tǒng)做了詳細介紹。首先,對無源時差定位系統(tǒng)的總體實現(xiàn)框架進行了詳細闡述。信號被數(shù)字板接收后,通過GSP打時間戳的方式產(chǎn)生精確授時數(shù)據(jù)并傳送給DSP,DSP對數(shù)據(jù)進行接收、解析、打包后發(fā)送給上位機,,最后上位機利用收到的精確授時數(shù)據(jù)進行時差估計及定位。無源時差定位系統(tǒng)的通信機制十分關(guān)鍵,然后本文對數(shù)據(jù)的通信機制也做了詳細描述。DSP作為FPGA與上位機的通信樞紐,起著非常重要的橋梁作用,因而最后本文介紹了在精確授時模式下DSP是如何通過多線程程序機制實現(xiàn)多任務(wù)的并發(fā)執(zhí)行,維護著整個系統(tǒng)有條不紊的工作。 最后對無源時差定位系統(tǒng)進行了聯(lián)調(diào)測試,并通過調(diào)試軟件對數(shù)據(jù)進行了比較分析。實驗結(jié)果表明:系統(tǒng)的數(shù)據(jù)通信機制、DSP的多線程程序機制都能正常運行;當(dāng)系統(tǒng)采用同源時鐘,真實時延為0ns時,對通過信號源產(chǎn)生的調(diào)制中頻信號進行時延估計,能夠得到誤差小于100ns的精確時延估計結(jié)果。
[Abstract]:With the development of global electronic information technology, GPS (Global Position Systems) technology is becoming more and more mature, which provides a good platform for passive time difference estimation. Because the passive time difference location technology is obviously superior to the active location technology in many aspects, the passive time difference location technology has been paid more and more attention, and has become the focus of many scholars at home and abroad. This paper focuses on how to realize passive time difference location system. Firstly, the passive time difference estimation and passive time difference location algorithm are introduced theoretically, and a large number of Matlab simulation studies are carried out for different simulation environments. Through the simulation results, the algorithm is compared and analyzed from the mean value and mean square error. Finally, the joint time delay estimation algorithm and joint time difference location algorithm are discussed. The Matlab simulation results show that the joint time delay estimation algorithm accelerates the convergence speed of the algorithm and greatly reduces the filter order of EDTE, which is beneficial to engineering implementation. Joint time difference (JTD) localization algorithm improves the location accuracy, and can estimate the target position accurately even when the TDOA error is large, while avoiding the non-convergence of the algorithm. Then this paper introduces how to realize passive time difference location system in detail. Firstly, the overall implementation framework of passive time difference location system is described in detail. After the signal is received by the digital board, the accurate timing data is generated by GSP timestamp and transmitted to the DSP,DSP to receive, parse, package and send to the host computer. Finally, the upper computer uses the received accurate timing data to estimate and locate the time difference. The communication mechanism of passive time difference location system is very important, and then the communication mechanism of data is described in detail. As a communication hub between FPGA and host computer, DSP plays a very important role as a bridge. In the end, this paper introduces how DSP implements multitasking concurrent execution through multithreading program mechanism in precise timing mode, and maintains the systematic work of the whole system. Finally, the passive time difference positioning system is tested, and the data is compared and analyzed by debugging software. The experimental results show that the data communication mechanism of the system and the multithreaded program mechanism of DSP can all work normally. When the system adopts the homologous clock and the real time delay is 0ns, the delay estimation of the modulation intermediate frequency signal generated by the signal source can obtain the accurate time delay estimation results with an error less than that of the 100ns.
【學(xué)位授予單位】:電子科技大學(xué)
【學(xué)位級別】:碩士
【學(xué)位授予年份】:2013
【分類號】:P228.4

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