在大多數(shù)的電子系統(tǒng)中,由于供電意外關(guān)閉造成數(shù)據(jù)丟失的情況時有發(fā)生。尤其隨著信息技術(shù)的快速發(fā)展,電子系統(tǒng)承載的數(shù)據(jù)規(guī)模不斷增大,數(shù)據(jù)丟失可能會造成巨大的經(jīng)濟(jì)損失,而且中斷后恢復(fù)數(shù)據(jù)難度大,需要耗費大量的時間和金錢。采用先進(jìn)的數(shù)據(jù)保護(hù)技術(shù)可以大大減少中斷帶來的風(fēng)險。如何解決意外斷電或者供電不穩(wěn)定時的數(shù)據(jù)丟失問題也成為近些年的重要研究課題。目前主流的解決方案是利用數(shù)據(jù)備份技術(shù),將運行數(shù)據(jù)保存在非易失性存儲器中,從而最大限度地減少因電源中斷造成的負(fù)面影響。然而這種數(shù)據(jù)備份技術(shù),數(shù)據(jù)保存過程復(fù)雜,數(shù)據(jù)傳輸速度受系統(tǒng)結(jié)構(gòu)與存儲類型限制。隨著新型非易失性器件的出現(xiàn),這種問題有了新的解決方案。觸發(fā)器是構(gòu)成時序電路的基本邏輯單元,也是計算機(jī),通信和其他類型數(shù)字電子系統(tǒng)的重要單元電路。觸發(fā)器是典型的易失性器件,在電源中斷的情況下,存儲在觸發(fā)器中的數(shù)據(jù)將消失。如果觸發(fā)器具有非易失性,即掉電后依舊能夠保持掉電前的狀態(tài),則整個系統(tǒng)也可以實現(xiàn)瞬態(tài)的數(shù)據(jù)恢復(fù)。隨著各種非易失器件的興起,研究者們提出了各種基于新器件的觸發(fā)器電路使觸發(fā)器具有非易失功能。其主要思想是在斷電時將觸發(fā)器內(nèi)容存儲在非易失性電路中,上電后從非易失...

【文章頁數(shù)】：63 頁

【學(xué)位級別】：碩士

【文章目錄】：
摘要
Abstract
Acknowledgement
Nomenclature
Chapter1 Introduction
    1.1 Necessarity for Nonvolatile Memory
    1.2 Application of Memristor in Nonvolatile Memory
    1.3 Application of Memristor in Scan Design
    1.4 Motivations and Objectives
    1.5 Organization of the Dissertation
Chapter2 Literature Review
    2.1 Memristor and its Model
    2.2 Memristor Applied in Latch and DFF
        2.2.1 Traditional D Latch and DFF
        2.2.2 Memristor-based D Latch and DFF
    2.3 The Application of Memristor in Scan Design
        2.3.1 Scan Design in VLSI
        2.3.2 Scan Flip-Flop and Scan Hold Flip-Flop
        2.3.3 Memristor-based Scan Design
    2.4 Summary
Chapter3 Memristor-based D Latch and DFF Design
    3.1 The Structure of the Proposed D Latch Design
        3.1.1 Analysis of the Proposed D Latch Design
        3.1.2 Simulation Result of D Latch
    3.2 D type Master-slave Flip-Flop
        3.2.1 The Proposed Master-slave DFF Design
        3.2.2 The Simulation of the Proposed Master-slave DFF Design
        3.2.3 Performance Analysis of the Proposed DFF
    3.3 Summary
Chapter4 Application of Memristor-based DFF in Scan Design
    4.1 The Design of the Scan Flip-Flop
        4.1.1 The Proposed Scan Flip-Flop
        4.1.2 Simulation Result of the Proposed SFF
    4.2 The Design of Scan Hold Flip-Flop
        4.2.1 The Proposed Scan Hold Flip-Flop
        4.2.2 Simulation Result of the Proposed SHFF
    4.3 The Design Evaluation and Analysis
        4.3.1 Analysis of Hardware Overhead
        4.3.2 Analysis of Power
        4.3.3 Analysis of Delay
    4.4 Summary
Conclusions
References
Author’s Publications



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