【摘要】：隨著摩爾定律的發(fā)展,數(shù)字集成電路的工藝節(jié)點已經(jīng)達到超深亞微米,晶體管的長期可靠性問題由之前的經(jīng)時擊穿和電遷移逐漸轉(zhuǎn)變?yōu)樨撈珘簻囟绕貌环�(wěn)定性效應(yīng)和溝道熱載流子效應(yīng),伴隨著宇航探索的研究逐漸深入,總劑量電離輻射效應(yīng)與溝道熱載流子效應(yīng)的結(jié)合效應(yīng)表現(xiàn)出1+12的效果。以上三種器件級效應(yīng)都會帶來晶體管閾值電壓的變化,閾值電壓的變化則會改變數(shù)字集成電路的延時,引發(fā)時序問題。如何從器件級機理到晶體管級建模再到電路級時序分析跨層建模已成為電路級可靠性設(shè)計關(guān)注的重點。論文基于130nm CMOS工藝,對器件效應(yīng)對晶體管閾值電壓的影響進行了研究。介紹了器件NBTI效應(yīng)、CHC效應(yīng)和TID效應(yīng)的物理機理以及三種效應(yīng)的經(jīng)典解釋模型。根據(jù)學(xué)術(shù)界最新研究成果,結(jié)合數(shù)字電路的實際工作情況,以占空比作為變量,介紹了基于占空比的晶體管級NBTI長期動態(tài)模型以及CHC和TID結(jié)合效應(yīng)的長期動態(tài)模型。以工作十年為目標(biāo),計算出了NBTI效應(yīng)引起的PMOS閾值電壓漂移量在50mV~73mV,CHC和TID結(jié)合效應(yīng)的NMOS閾值電壓漂移量在77mV~220mV。論文以16×16的移位乘法器RTL代碼作為老化分析對象,在Design Complier中設(shè)置相關(guān)面積時序約束,通過邏輯綜合獲得網(wǎng)表,通過靜態(tài)時序分析獲得關(guān)鍵路徑,并在Encounter工具中完成布局、時鐘樹綜合以及布線工作,獲得了數(shù)字版圖以及完成物理設(shè)計后關(guān)鍵路徑時序的變化量。論文選用常見的一倍驅(qū)動反相器、兩輸入與非門以及兩輸入或非門作為研究對象,分析了占空比作為變量引起的閾值變化導(dǎo)致時序變化的規(guī)律,在Hspice中進行仿真獲得了占空比與電路延時的關(guān)系�；陟o態(tài)時序分析獲得的關(guān)鍵路徑,建立了關(guān)鍵路徑中組合邏輯標(biāo)準單元的老化時序庫,在此基礎(chǔ)上對RTL代碼重新進行了邏輯綜合和布局布線工作,獲得了基于老化時序庫的電路延時信息變化。分析結(jié)果表明,關(guān)鍵路徑組合邏輯延時在綜合階段增加了1.61ns,布局布線完成后增加了2.159ns,增加了10%。為抗老化降頻使用提供了合理的參考依據(jù)。
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圖片說明：Si-SiO2界面處存在的Si的懸掛鍵[5]
[Abstract]:With the development of Moore's law, the process nodes of digital integrated circuits have reached ultra-deep submicron. The long-term reliability of transistors has gradually changed from time breakdown and electromigration to negative bias temperature bias instability effect and channel hot carrier effect. With the deepening of aerospace exploration, the combination effect of total dose ionizing radiation effect and channel hot carrier effect shows the effect of 112. The above three device-level effects will lead to the change of transistor threshold voltage, while the change of threshold voltage will change the delay of digital integrated circuits and lead to timing problems. From device level mechanism to transistor level modeling to circuit level timing analysis, cross-layer modeling has become the focus of circuit level reliability design. Based on 130nm CMOS technology, the influence of device effect on transistor threshold voltage is studied in this paper. The physical mechanism of device NBTI effect, CHC effect and TID effect and the classical interpretation model of the three effects are introduced. According to the latest research results of academic circles and the actual working situation of digital circuits, the long-term dynamic model of crystal tube level NBTI based on duty cycle and the long-term dynamic model of the combination effect of CHC and TID are introduced. In order to work for ten years, the PMOS threshold voltage drift caused by NBTI effect is calculated to be 50mV 鈮，

本文編號：2512318