【摘要】：隨著芯片集成度的提高和芯片特征尺寸的縮小,在單個(gè)芯片中集成的核心數(shù)目已經(jīng)越來越多。片上網(wǎng)絡(luò)由于其擴(kuò)展性好、通信帶寬高等特點(diǎn),已經(jīng)成為目前片上多核系統(tǒng)核間主流互連方案。但隨著芯片特征尺寸的持續(xù)縮減,片上網(wǎng)絡(luò)的故障率受串?dāng)_、耦合、單粒子翻轉(zhuǎn)等因素的影響而持續(xù)增加,因此片上網(wǎng)絡(luò)的容錯(cuò)設(shè)計(jì)成為近年來一個(gè)重要的研究熱點(diǎn)。由于容錯(cuò)設(shè)計(jì)將不可避免的引入各種開銷,如何平衡可靠性和開銷就成為了核間通信體制的研究重點(diǎn)。本文對(duì)片上網(wǎng)絡(luò)鏈路上的瞬時(shí)故障進(jìn)行研究,提出了一套基于跨層設(shè)計(jì)的高可靠性核間通信體制。該體制不但可以有效提升核間通信的可靠性,而且不會(huì)引入過多的面積和功耗開銷。首先,本文對(duì)片上網(wǎng)絡(luò)的故障種類、故障成因及故障建模展開研究,指出現(xiàn)有片上網(wǎng)絡(luò)鏈路容錯(cuò)方法存在諸如開銷大等方面的問題。針對(duì)這些問題,本文采用了更合理、更直觀的比特故障模型來表征片上網(wǎng)絡(luò)的鏈路故障,并以該模型為基礎(chǔ)開展容錯(cuò)傳輸方案的研究和設(shè)計(jì)。其次,本文針對(duì)數(shù)據(jù)包的可達(dá)性問題,提出了一種基于跨層設(shè)計(jì)的包頭高可靠檢糾錯(cuò)方法,用于保護(hù)包頭中的關(guān)鍵路由信息。該容錯(cuò)設(shè)計(jì)主要由路由器中的輕量級(jí)檢錯(cuò)模塊、網(wǎng)絡(luò)接口中的糾錯(cuò)模塊以及相關(guān)的控制邏輯三部分組成。其中,包頭在數(shù)據(jù)鏈路層進(jìn)行檢錯(cuò),然后在傳輸層采用譯碼單元進(jìn)行糾錯(cuò),從而為包頭提供高可靠性,以保證數(shù)據(jù)包能夠到達(dá)正確的目的地。隨后,在數(shù)據(jù)包可達(dá)的基礎(chǔ)上,本文分析了片上網(wǎng)絡(luò)低開銷高可靠的優(yōu)化空間,對(duì)有效載荷進(jìn)行低開銷高可靠的容錯(cuò)設(shè)計(jì)。該設(shè)計(jì)采用(72,64)漢明碼在傳輸層對(duì)有效載荷檢錯(cuò)和糾錯(cuò),實(shí)現(xiàn)糾正1比特隨機(jī)錯(cuò)誤并檢測2比特差錯(cuò)的功能,以確保有效載荷的可靠性。在本文的最后使用ESYNET軟件仿真平臺(tái)以及Synopsys公司的EDA工具對(duì)上述容錯(cuò)設(shè)計(jì)進(jìn)行仿真驗(yàn)證,對(duì)數(shù)據(jù)包到達(dá)率、數(shù)據(jù)包平均時(shí)延、功耗和面積開銷等指標(biāo)進(jìn)行分析評(píng)估,并與其它常用傳輸機(jī)制進(jìn)行對(duì)比。由實(shí)驗(yàn)結(jié)果可知,本文提出的傳輸方案在保證核間通信高可靠性的同時(shí),減少了片上網(wǎng)絡(luò)硬件資源開銷和傳輸時(shí)間開銷,實(shí)現(xiàn)片上性能和開銷的良好平衡。
文內(nèi)圖片：
圖片說明：基于NoC的3×3同構(gòu)MPSoC結(jié)構(gòu)圖
[Abstract]:With the improvement of chip integration and the reduction of chip feature size, the number of cores integrated in a single chip has become more and more. Because of its good expansibility and high communication bandwidth, on-chip network has become the mainstream interconnection scheme between cores of on-chip multi-core system. However, with the continuous reduction of chip feature size, the failure rate of on-chip network is affected by crosstalk, coupling, single-particle flip and other factors, so the fault-tolerant design of on-chip network has become an important research focus in recent years. Because fault-tolerant design will inevitably introduce all kinds of overhead, how to balance reliability and overhead has become the research focus of inter-core communication system. In this paper, the instantaneous fault on-chip network link is studied, and a set of high reliability inter-core communication system based on cross-layer design is proposed. This scheme can not only effectively improve the reliability of inter-core communication, but also does not introduce too much area and power consumption overhead. Firstly, this paper studies the fault types, fault causes and fault modeling of on-chip network, and points out that the existing fault-tolerant methods of on-chip network link have some problems, such as high overhead and so on. In order to solve these problems, a more reasonable and intuitive bit fault model is used to characterize the link failure of on-chip network, and the fault-tolerant transmission scheme is studied and designed on the basis of this model. Secondly, in order to solve the problem of packet reachability, a highly reliable detection and error correction method based on cross-layer design is proposed to protect the key routing information in the packet header. The fault-tolerant design is mainly composed of lightweight error detection module in router, error correction module in network interface and related control logic. Among them, the packet head detects errors in the data link layer, and then uses the decoding unit to correct the error in the transmission layer, thus providing high reliability for the packet header to ensure that the packet can reach the correct destination. Then, on the basis of packet accessibility, this paper analyzes the low overhead and high reliability optimization space of on-chip network, and carries out the fault-tolerant design of low overhead and high reliability for payloads. In this design, (72, 64) hamming codes are used to correct and correct payloads in the transport layer, so as to correct 1 bit random errors and detect 2 bits errors, so as to ensure the reliability of payloads. At the end of this paper, the ESYNET software simulation platform and Synopsys EDA tool are used to simulate and verify the fault-tolerant design, and the packet arrival rate, average packet delay, power consumption and area overhead are analyzed and evaluated, and compared with other common transmission mechanisms. The experimental results show that the transmission scheme proposed in this paper not only ensures the high reliability of inter-core communication, but also reduces the hardware resource overhead and transmission time overhead of on-chip network, and realizes a good balance between on-chip performance and overhead.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN47

【參考文獻(xiàn)】

相關(guān)期刊論文 前1條

1 薛挺;賀興華;張開鋒;張哲;;具有64位數(shù)據(jù)檢糾錯(cuò)功能的FPGA模塊設(shè)計(jì)[J];現(xiàn)代電子技術(shù);2009年06期

相關(guān)博士學(xué)位論文 前2條

1 付方發(fā);基于片上網(wǎng)絡(luò)的MPSoC關(guān)鍵技術(shù)研究[D];哈爾濱工業(yè)大學(xué);2012年

2 李磊;片上網(wǎng)絡(luò)NoC的通信研究[D];浙江大學(xué);2007年

相關(guān)碩士學(xué)位論文 前4條

1 張曉帆;片上網(wǎng)絡(luò)控制邏輯容錯(cuò)方法研究[D];電子科技大學(xué);2016年

2 許相臺(tái);網(wǎng)絡(luò)編碼在傳輸層的應(yīng)用研究[D];哈爾濱工業(yè)大學(xué);2010年

3 陳亮;基于ASIC的直接數(shù)字頻率合成器前端設(shè)計(jì)與實(shí)現(xiàn)[D];武漢科技大學(xué);2008年

4 姚力;SOC中高性能低功耗總線通信結(jié)構(gòu)設(shè)計(jì)[D];上海交通大學(xué);2007年

，

本文編號(hào)：2512132