基于55nm工藝的12位高速低功耗流水線型ADC設計
發(fā)布時間：2019-07-05 15:24
【摘要】：隨著通信及消費類電子的迅速發(fā)展,SOC(system-on-a-chip)片上系統(tǒng)得到了廣泛應用。如今便攜式電子設備逐漸深入人們的生活,SOC中集成的功能也越來越復雜和強大,因此低功耗高性能集成電路設計已經(jīng)逐漸成為研究的重點和熱點。近年來,半導體工藝特征尺寸大幅減小,這大幅提升了MOS晶體管的本征頻率、降低了電路的功耗并有效提高了電路的集成度。然而工藝尺寸的減小也導致了器件的本征增益下降、供電電壓降低等各種問題,從而加大了模擬集成電路的設計難度。這些問題在模數(shù)轉(zhuǎn)換器的設計中尤為突出。因此,在現(xiàn)代SOC應用和工藝條件下設計一款滿足低功耗高性能要求的ADC已成為一項巨大的挑戰(zhàn)。本設計針對視頻模擬前端的系統(tǒng)需求,基于HLMC 55nm CMOS混合信號工藝設計了一款低功耗12bit采樣速率為160M/s的流水線型ADC。論文首先分析了衡量流水線型ADC的關鍵性能參數(shù)和影響系統(tǒng)性能的非理想性的來源,在此基礎之上重點考察了目前業(yè)內(nèi)常用的低功耗技術。在比較了各種技術之后選用了運放共享、嵌套gain boost運放、電容逐級遞減等技術。然后根據(jù)這些技術對流水線型模數(shù)轉(zhuǎn)換器進行了系統(tǒng)級分析、設計和規(guī)劃,隨后完成了晶體管級電路設計。最后基于深亞微米工藝版圖設計思想完成了本課題的版圖工作,后仿真結果表明在采樣頻率為160M/s,輸入信號為39.1MHz的正弦信號情況下,該ADC的SFDR為83.05dB,SNDR為72.1dB,ENOB達到11.68bit,而功耗只有54mW,整體性能指標完全滿足系統(tǒng)的預期設計要求。論文研究成果均基于深亞微米工藝完成,其對深亞微米下模擬集成電路設計,尤其是對混合信號電路設計及其相關版圖繪制均具有良好的參考價值。此外,論文對pipelined ADC的低功耗設計也進行了深入分析,對SOC系統(tǒng)中低功耗應用的設計具有一定的參考意義和價值。
[Abstract]:With the rapid development of communication and consumer electronics, SOC (system-on-a-chip) on-chip system has been widely used. Nowadays, portable electronic devices are gradually deepening into people's lives, and the integration function in SOC is becoming more and more complex and powerful, so the design of low power consumption and high performance integrated circuits has gradually become the focus and focus of research. In recent years, the characteristic size of semiconductor process has been greatly reduced, which greatly improves the intrinsic frequency of MOS transistors, reduces the power consumption of the circuit and effectively improves the integration of the circuit. However, the reduction of process size also leads to the decrease of intrinsic gain and power supply voltage of the device, which makes the design of analog integrated circuit more difficult. These problems are particularly prominent in the design of analog-to-digital converter. Therefore, it has become a great challenge to design a ADC to meet the requirements of low power consumption and high performance under modern SOC applications and process conditions. In order to meet the system requirements of video analog front end, a streamline ADC. with low power consumption 12bit sampling rate of 160M/s is designed based on HLMC 55nm CMOS mixed signal process. Firstly, this paper analyzes the key performance parameters of streamline ADC and the sources of non-ideality that affect the performance of the system, and on this basis, focuses on the low power consumption technologies commonly used in the industry at present. After comparing all kinds of technologies, operational amplifier sharing, embedded gain boost operational amplifier, capacitance decreasing and so on are selected. Then, according to these technologies, the streamline analog-to-digital converter is analyzed, designed and planned at the system level, and then the transistor-level circuit design is completed. Finally, based on the deep submicron process layout design idea, the post-simulation results show that when the sampling frequency is 160m 鈮，
本文編號：2510621
[Abstract]:With the rapid development of communication and consumer electronics, SOC (system-on-a-chip) on-chip system has been widely used. Nowadays, portable electronic devices are gradually deepening into people's lives, and the integration function in SOC is becoming more and more complex and powerful, so the design of low power consumption and high performance integrated circuits has gradually become the focus and focus of research. In recent years, the characteristic size of semiconductor process has been greatly reduced, which greatly improves the intrinsic frequency of MOS transistors, reduces the power consumption of the circuit and effectively improves the integration of the circuit. However, the reduction of process size also leads to the decrease of intrinsic gain and power supply voltage of the device, which makes the design of analog integrated circuit more difficult. These problems are particularly prominent in the design of analog-to-digital converter. Therefore, it has become a great challenge to design a ADC to meet the requirements of low power consumption and high performance under modern SOC applications and process conditions. In order to meet the system requirements of video analog front end, a streamline ADC. with low power consumption 12bit sampling rate of 160M/s is designed based on HLMC 55nm CMOS mixed signal process. Firstly, this paper analyzes the key performance parameters of streamline ADC and the sources of non-ideality that affect the performance of the system, and on this basis, focuses on the low power consumption technologies commonly used in the industry at present. After comparing all kinds of technologies, operational amplifier sharing, embedded gain boost operational amplifier, capacitance decreasing and so on are selected. Then, according to these technologies, the streamline analog-to-digital converter is analyzed, designed and planned at the system level, and then the transistor-level circuit design is completed. Finally, based on the deep submicron process layout design idea, the post-simulation results show that when the sampling frequency is 160m 鈮，
本文編號：2510621
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