一種基于跟蹤式量化器的高性能Delta-Sigma ADC的研究與實現(xiàn)
發(fā)布時間：2019-06-20 23:29
【摘要】：隨著現(xiàn)代信息技術的高速發(fā)展以及移動終端設備的普及,高速、高精度和低功耗的信息處理設備成為市場的熱門需求。Delta-Sigma ADC具有精度高、硬件開銷低等特點被廣泛使用在移動便攜式設備中。但是Delta-Sigma ADC的速度受限問題成為制約其發(fā)展的瓶頸,因此如何提高其速度成為研究的熱點。 本文在傳統(tǒng)前饋結構多比特量化Delta-Sigma ADC的基礎上,探索了基于跟蹤式量化器的設計。與傳統(tǒng)量化器不同,跟蹤式量化器只量化當前輸入和上次輸入的殘差,來有效降低量化器的輸入擺幅,從而減少比較次數(shù),降低功耗,提高轉換速度,并在數(shù)字域中通過積分來恢復當前輸入的大小。系統(tǒng)前饋結構的設計使得積分器只需要處理量化噪聲,極大地降低了積分環(huán)路的信號擺幅。將量化比特數(shù)提高到8比特,進一步降低了量化噪聲,從而進一步降低運放的設計要求降低功耗。數(shù)據(jù)加權平均技術被應用在反饋回路中減小多比特量化引起的非線性,從而保證系統(tǒng)的信號噪聲失真比不降低(Signal to Noise and Distortion Ratio, SNDR).通過數(shù)學計算和Matlab建模仿真確定系統(tǒng)架構,并總結了一套完整的設計方法�？紤]實際電路中的各種非理想因數(shù),比如：運放的有限帶寬、壓擺率和直流增益等,并且分別對它們進行建模,再帶入系統(tǒng)中進行仿真,最終為實際電路的參數(shù)設計提供依據(jù)。 8位跟蹤式ADC中的DAC采用單調開關結構不僅節(jié)省了50%的電容,而且大幅降低了功耗。文中對傳統(tǒng)雙尾電流管結構的比較器進行了改進使其具有更低的失調電壓和噪聲,并且該結構只需要單相時鐘控制,因此改進后的比較器也降低了對時鐘產生電路的要求。在0.6V下采樣開關采用自舉技術不僅可以提高采樣開關的線性度還可以增大允許的輸入信號擺幅。本文還對傳統(tǒng)的自舉開關電路進行了優(yōu)化,用PMOS管代替?zhèn)鹘y(tǒng)結構中的NMOS管,避免使用電容結構的電荷倍壓器所帶來的高功耗和大面積。 該款Delta-Sigma ADC采用了TSMC130m1P8M的標準CMOS工藝,工作在0.6V電壓下,帶寬為50kHz,過采樣率為16,SNDR達到了76.8dB,核心電路的功耗為152.2μW,品質因數(shù)(Figure of Merit,FoM)為0.26pJ/step。芯片核心面積為0.25mm2。
[Abstract]:With the rapid development of modern information technology and the popularity of mobile terminal equipment, high-speed, high-precision and low-power information processing equipment has become a hot demand in the market. Delta-Sigma ADC is widely used in mobile portable devices because of its high precision and low hardware overhead. However, the speed constraint of Delta-Sigma ADC has become the bottleneck of its development, so how to improve its speed has become the focus of research. Based on the traditional feedforward structure multi-bit quantitative Delta-Sigma ADC, the design of tracking-based quantizer is explored in this paper. Different from the traditional quantizer, the tracking quantizer only quantifies the residual between the current input and the last input, so as to effectively reduce the input swing of the quantizer, thus reducing the number of comparisons, reducing power consumption, improving the conversion speed, and restoring the current input size through integration in the digital domain. The design of the feedforward structure of the system makes the Integrator only need to deal with the quantitative noise, which greatly reduces the signal swing of the integral loop. The quantized bit number is increased to 8 bits, and the quantization noise is further reduced, thus the design requirements of operational amplifier are further reduced to reduce the power consumption. The data weighted average technique is applied to the feedback loop to reduce the nonlinear caused by multi-bit quantification, so as to ensure that the signal noise distortion ratio of the system does not reduce the (Signal to Noise and Distortion Ratio, SNDR). The system architecture is determined by mathematical calculation and Matlab modeling and simulation, and a set of complete design methods are summarized. Considering all kinds of non-ideal factors in the actual circuit, such as the limited bandwidth, pendulum rate and DC gain of the operational amplifier, and modeling them respectively, and then bringing them into the system for simulation, finally providing the basis for the parameter design of the actual circuit. The monotone switching structure of DAC in 8-bit tracking ADC not only saves 50% capacitance, but also greatly reduces power consumption. In this paper, the comparator of the traditional double-tailed current tube structure is improved to have lower misalignment voltage and noise, and the structure only needs single-phase clock control, so the improved comparator also reduces the requirement of clock generation circuit. At 0.6 V, the bootstrap technique can not only improve the linearity of the sampling switch, but also increase the allowable swing of the input signal. The traditional bootstrap switch circuit is also optimized in this paper. PMOS transistor is used instead of NMOS transistor in traditional structure to avoid the high power consumption and large area caused by the charge multiplier with capacitance structure. The Delta-Sigma ADC adopts the standard CMOS process of TSMC130m1P8M, operating at 0.6 V voltage, the bandwidth is 50 Hz, the over-sampling rate is 16, the SNDR reaches 76.8dB, the power consumption of the core circuit is 152.2 渭 W, and the quality factor (Figure of Merit,FoM is 0.26pJ 鈮，
本文編號：2503602
[Abstract]:With the rapid development of modern information technology and the popularity of mobile terminal equipment, high-speed, high-precision and low-power information processing equipment has become a hot demand in the market. Delta-Sigma ADC is widely used in mobile portable devices because of its high precision and low hardware overhead. However, the speed constraint of Delta-Sigma ADC has become the bottleneck of its development, so how to improve its speed has become the focus of research. Based on the traditional feedforward structure multi-bit quantitative Delta-Sigma ADC, the design of tracking-based quantizer is explored in this paper. Different from the traditional quantizer, the tracking quantizer only quantifies the residual between the current input and the last input, so as to effectively reduce the input swing of the quantizer, thus reducing the number of comparisons, reducing power consumption, improving the conversion speed, and restoring the current input size through integration in the digital domain. The design of the feedforward structure of the system makes the Integrator only need to deal with the quantitative noise, which greatly reduces the signal swing of the integral loop. The quantized bit number is increased to 8 bits, and the quantization noise is further reduced, thus the design requirements of operational amplifier are further reduced to reduce the power consumption. The data weighted average technique is applied to the feedback loop to reduce the nonlinear caused by multi-bit quantification, so as to ensure that the signal noise distortion ratio of the system does not reduce the (Signal to Noise and Distortion Ratio, SNDR). The system architecture is determined by mathematical calculation and Matlab modeling and simulation, and a set of complete design methods are summarized. Considering all kinds of non-ideal factors in the actual circuit, such as the limited bandwidth, pendulum rate and DC gain of the operational amplifier, and modeling them respectively, and then bringing them into the system for simulation, finally providing the basis for the parameter design of the actual circuit. The monotone switching structure of DAC in 8-bit tracking ADC not only saves 50% capacitance, but also greatly reduces power consumption. In this paper, the comparator of the traditional double-tailed current tube structure is improved to have lower misalignment voltage and noise, and the structure only needs single-phase clock control, so the improved comparator also reduces the requirement of clock generation circuit. At 0.6 V, the bootstrap technique can not only improve the linearity of the sampling switch, but also increase the allowable swing of the input signal. The traditional bootstrap switch circuit is also optimized in this paper. PMOS transistor is used instead of NMOS transistor in traditional structure to avoid the high power consumption and large area caused by the charge multiplier with capacitance structure. The Delta-Sigma ADC adopts the standard CMOS process of TSMC130m1P8M, operating at 0.6 V voltage, the bandwidth is 50 Hz, the over-sampling rate is 16, the SNDR reaches 76.8dB, the power consumption of the core circuit is 152.2 渭 W, and the quality factor (Figure of Merit,FoM is 0.26pJ 鈮，
本文編號：2503602
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