2.5Gbps串行接口發(fā)送端設(shè)計
發(fā)布時間：2019-06-12 00:53
【摘要】：隨著信息產(chǎn)業(yè)的不斷發(fā)展，各類電子產(chǎn)品不斷涌現(xiàn)，人們的生活水準日益提高。計算機中處理器處理能力的不斷提高，龐大的數(shù)據(jù)量暢通無阻的高速傳輸已經(jīng)成為支撐信息產(chǎn)業(yè)發(fā)展的關(guān)鍵環(huán)節(jié)。伴隨著串行接口技術(shù)的出現(xiàn)，突破了并行接口關(guān)于速率的瓶頸，成功的緩解了高速數(shù)據(jù)通信行業(yè)的數(shù)據(jù)傳輸問題。隨著傳輸速率的不斷提高，各類串行接口也相繼出現(xiàn)，基于LVDS、VML、CML等技術(shù)的接口芯片大量生產(chǎn)。但串行接口中存在的問題也嚴重影響高速數(shù)據(jù)傳輸?shù)钠焚|(zhì)。其中，信道的高頻損耗已經(jīng)成為限制高速數(shù)據(jù)傳輸系統(tǒng)性能的關(guān)鍵因素。另外，電路設(shè)計中的其他非理想因素同樣也是影響高速傳輸?shù)闹匾蛩�。因此，設(shè)計者需要深入的了解這些問題并做出解決方案。 本文中針對高速互連系統(tǒng)中的關(guān)鍵性問題進行了深入的研究，并完成了接口電路中發(fā)送端部分的設(shè)計。首先，對互連信道的特性進行了分析并建立了信道模型。其次，對高速互連系統(tǒng)中存在的信號完整性進行了分析，詳細介紹了數(shù)據(jù)傳輸鏈路上存在的非理想因素并給出了解決的方法。然后，簡單介紹了幾種目前業(yè)界內(nèi)廣泛使用的LVDS、VML、CML等接口電路，確定了基于SMIC180nm工藝采用CML技術(shù)實現(xiàn)2.5Gbps傳輸速率的方案，，詳細的分析了業(yè)界內(nèi)針對信道的高頻損耗所采用的均衡技術(shù)原理并提出了本設(shè)計中所采用的預(yù)加重技術(shù)。最后詳細的給出了發(fā)送端整體電路的設(shè)計并完成了相應(yīng)版圖的繪制。在Cadence平臺下，利用Spectre仿真器對各模塊電路以及整體電路進行了仿真并給出了相應(yīng)的前仿真和后仿真結(jié)果。 在本文最后一章對論文作出了總結(jié)，提出了本設(shè)計中仍存在的一些問題并給出了解決方案。
[Abstract]:With the continuous development of information industry, all kinds of electronic products continue to emerge, and people's living standards are improving day by day. With the continuous improvement of processor processing ability in computer, the unimpeded and high-speed transmission of huge amount of data has become the key link to support the development of information industry. With the emergence of serial interface technology, the bottleneck of parallel interface about rate has been broken through, and the problem of data transmission in high-speed data communication industry has been alleviated successfully. With the continuous increase of transmission rate, all kinds of serial interfaces have appeared one after another, and the interface chips based on LVDS,VML,CML and other technologies are produced in large quantities. However, the problems existing in serial interface also seriously affect the quality of high-speed data transmission. Among them, the high frequency loss of the channel has become the key factor to limit the performance of high speed data transmission system. In addition, other non-ideal factors in circuit design are also important factors affecting high-speed transmission. Therefore, designers need to have an in-depth understanding of these problems and make solutions. In this paper, the key problems in high-speed interconnection system are deeply studied, and the design of the transmitter in the interface circuit is completed. Firstly, the characteristics of interconnect channel are analyzed and the channel model is established. Secondly, the signal integrity in the high-speed interconnection system is analyzed, the non-ideal factors existing in the data transmission link are introduced in detail, and the solutions are given. Then, several interface circuits such as LVDS,VML,CML, which are widely used in the industry, are briefly introduced, and the scheme of using CML technology to realize the transmission rate of 2.5Gbps based on SMIC180nm process is determined. the principle of equalization technology used in the industry for the high frequency loss of the channel is analyzed in detail, and the preweighting technology used in this design is put forward. Finally, the design of the whole circuit at the transmitter is given in detail and the corresponding layout is drawn. On Cadence platform, each module circuit and the whole circuit are simulated by Spectre simulator, and the corresponding pre-simulation and post-simulation results are given. In the last chapter of this paper, the paper is summarized, some problems still exist in this design are put forward and the solutions are given.
【學(xué)位授予單位】：北京理工大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN402
本文編號：2497590
[Abstract]:With the continuous development of information industry, all kinds of electronic products continue to emerge, and people's living standards are improving day by day. With the continuous improvement of processor processing ability in computer, the unimpeded and high-speed transmission of huge amount of data has become the key link to support the development of information industry. With the emergence of serial interface technology, the bottleneck of parallel interface about rate has been broken through, and the problem of data transmission in high-speed data communication industry has been alleviated successfully. With the continuous increase of transmission rate, all kinds of serial interfaces have appeared one after another, and the interface chips based on LVDS,VML,CML and other technologies are produced in large quantities. However, the problems existing in serial interface also seriously affect the quality of high-speed data transmission. Among them, the high frequency loss of the channel has become the key factor to limit the performance of high speed data transmission system. In addition, other non-ideal factors in circuit design are also important factors affecting high-speed transmission. Therefore, designers need to have an in-depth understanding of these problems and make solutions. In this paper, the key problems in high-speed interconnection system are deeply studied, and the design of the transmitter in the interface circuit is completed. Firstly, the characteristics of interconnect channel are analyzed and the channel model is established. Secondly, the signal integrity in the high-speed interconnection system is analyzed, the non-ideal factors existing in the data transmission link are introduced in detail, and the solutions are given. Then, several interface circuits such as LVDS,VML,CML, which are widely used in the industry, are briefly introduced, and the scheme of using CML technology to realize the transmission rate of 2.5Gbps based on SMIC180nm process is determined. the principle of equalization technology used in the industry for the high frequency loss of the channel is analyzed in detail, and the preweighting technology used in this design is put forward. Finally, the design of the whole circuit at the transmitter is given in detail and the corresponding layout is drawn. On Cadence platform, each module circuit and the whole circuit are simulated by Spectre simulator, and the corresponding pre-simulation and post-simulation results are given. In the last chapter of this paper, the paper is summarized, some problems still exist in this design are put forward and the solutions are given.
【學(xué)位授予單位】：北京理工大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN402
【參考文獻】
相關(guān)期刊論文 前4條
1 康翔;張卜瑞;;高速I/O接口技術(shù)[J];電子工程師;2008年05期
2 霍衛(wèi)濤;邵剛;李攀;李哲;;高速SerDes抖動成因及其測試方法分析[J];計算機光盤軟件與應(yīng)用;2012年02期
3 曉輝;;速度快10倍——走進USB 3.0標準[J];電腦知識與技術(shù)(經(jīng)驗技巧);2010年03期
4 董慧娟;高速串行鏈路的信號均衡技術(shù)[J];計算機工程;2005年22期
相關(guān)博士學(xué)位論文 前1條
1 韋雪明;高速SERDES接口芯片設(shè)計關(guān)鍵技術(shù)研究[D];電子科技大學(xué);2012年
本文編號：2497590
本文鏈接：http://sikaile.net/kejilunwen/dianzigongchenglunwen/2497590.html
最近更新
教材專著
