【摘要】：隨著我國(guó)集成電路行業(yè)的迅猛發(fā)展,以及集成電路產(chǎn)品日漸深入到我們的日常生活中,基于集成電路設(shè)計(jì)流程的可信性方法研究也成了前沿性的研究課題。可信性設(shè)計(jì)方法的研究主要涉及到設(shè)計(jì)流程和可信性兩個(gè)方面,本文從集成電路的設(shè)計(jì)流程出發(fā),分析了RTL級(jí)硬件木馬的結(jié)構(gòu)和工作特性,研究了貫穿整個(gè)設(shè)計(jì)流程的DFT技術(shù),并提出了如何利用DFT技術(shù)來(lái)檢測(cè)和判定硬件木馬的位置。本文主要工作內(nèi)容如下:第一,對(duì)硬件木馬的結(jié)構(gòu)特性以及工作特點(diǎn)進(jìn)行了詳細(xì)分析,并對(duì)當(dāng)前已出現(xiàn)的硬件木馬檢測(cè)方法進(jìn)行了分析、對(duì)比、歸納,然后列舉了每種檢測(cè)方法的優(yōu)缺點(diǎn)。第二,深入研究了RTL級(jí)硬件木馬的工作和結(jié)構(gòu)特點(diǎn),通過(guò)分析基于Verilog語(yǔ)言的RTL級(jí)硬件木馬的結(jié)構(gòu)特點(diǎn),以及對(duì)AES基準(zhǔn)電路的分析,建立了RTL級(jí)硬件木馬檢測(cè)的可信模型,并提出了利用Perl語(yǔ)言完成RTL級(jí)硬件木馬的檢測(cè)方法,并通過(guò)其他攻擊者設(shè)計(jì)的木馬進(jìn)行了驗(yàn)證,該方法不僅簡(jiǎn)單有效而且彌補(bǔ)了傳統(tǒng)檢測(cè)方法和UCI檢測(cè)方法的不足。第三,深入研究了可測(cè)性設(shè)計(jì)技術(shù)及其實(shí)施的各個(gè)階段,提出了基于DFT技術(shù)的硬件木馬檢測(cè)方法。通過(guò)對(duì)基準(zhǔn)電路插入掃描鏈前后的數(shù)據(jù)進(jìn)行分析發(fā)現(xiàn),掃描鏈的插入可以放大硬件木馬的活動(dòng)1.4倍以上;通過(guò)對(duì)不同工藝下掃描鏈激活前后的參數(shù)進(jìn)行對(duì)比發(fā)現(xiàn):在SMIC130nm工藝條件下掃描鏈的插入使木馬檢測(cè)準(zhǔn)確率提高了65%,在SMIC90nm條件下提升了49%。最后詳細(xì)分析了造成結(jié)果變化的原因并在此基礎(chǔ)上進(jìn)一步提出了硬件木馬的定位方法。第四,更進(jìn)一步的分析了基于DFT技術(shù)的硬件木馬定位技術(shù),首先闡述了實(shí)驗(yàn)的整個(gè)流程和使用的不同木馬結(jié)構(gòu),然后通過(guò)添加不同數(shù)量的掃描鏈之后,分析局部激活和全局激活掃描鏈時(shí)對(duì)電路所帶來(lái)的影響發(fā)現(xiàn):單獨(dú)激活含有木馬的掃描鏈可以使電路的整體平均功耗增加1.7倍以上,峰值功耗增加1.8倍以上,并通過(guò)實(shí)驗(yàn)證明了可以通過(guò)該方式找到硬件木馬所在的大概位置。
[Abstract]:With the rapid development of integrated circuit industry in our country and the deepening of integrated circuit products into our daily life, the research on credibility method based on integrated circuit design process has become a leading research topic. The research of credibility design method mainly involves two aspects: design flow and credibility. Based on the design flow of integrated circuit, this paper analyzes the structure and working characteristics of RTL level hardware Trojan horse, and studies the DFT technology that runs through the whole design process. How to use DFT technology to detect and determine the location of hardware Trojan horse is put forward. The main contents of this paper are as follows: first, the structural characteristics and working characteristics of the hardware Trojan horse are analyzed in detail, and the detection methods of the hardware Trojan horse are analyzed, compared and summarized. Then the advantages and disadvantages of each detection method are listed. Secondly, the work and structure characteristics of RTL level hardware Trojan horse are deeply studied. By analyzing the structural characteristics of RTL level hardware Trojan horse based on Verilog language and the analysis of AES reference circuit, the trusted model of RTL level hardware Trojan horse detection is established. The detection method of RTL level hardware Trojan horse is proposed and verified by other Trojans designed by other attackers. This method is not only simple and effective, but also makes up for the shortcomings of traditional detection methods and UCI detection methods. Thirdly, the testability design technology and its implementation stages are deeply studied, and the hardware Trojan horse detection method based on DFT technology is proposed. Through the analysis of the data before and after the reference circuit is inserted into the scanning chain, it is found that the insertion of the scan chain can amplify the activity of the hardware Trojan horse more than 1.4 times. By comparing the parameters before and after the activation of scanning chain under different processes, it is found that the insertion of scanning chain under SMIC130nm process improves the detection accuracy of Trojan horse by 65% and 49% under SMIC90nm condition. Finally, the causes of the change of results are analyzed in detail, and the location method of hardware Trojan horse is further put forward. Fourth, the hardware Trojan horse location technology based on DFT technology is further analyzed. Firstly, the whole process of the experiment and the different Trojan horse structures used are described, and then by adding different number of scanning chains, By analyzing the influence of local activation and global activation of scan chain on the circuit, it is found that activating the scan chain containing Trojan horse alone can increase the overall average power consumption of the circuit by more than 1.7 times and the peak power consumption by more than 1.8 times. The experimental results show that the approximate location of the hardware Trojan horse can be found by this method.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN402

【參考文獻(xiàn)】

相關(guān)期刊論文 前7條

1 趙志勛;倪林;李少青;;硬件木馬電路功耗的檢測(cè)方法[J];北京郵電大學(xué)學(xué)報(bào);2015年04期

2 張鵬;王新成;周慶;;基于投影尋蹤分析的芯片硬件木馬檢測(cè)[J];通信學(xué)報(bào);2013年04期

3 劉長(zhǎng)龍;趙毅強(qiáng);史亞峰;馮紫竹;;基于側(cè)信道分析的硬件木馬建模與優(yōu)化[J];華中科技大學(xué)學(xué)報(bào)(自然科學(xué)版);2013年02期

4 鄭朝霞;韓玲;李陽(yáng);鄒雪城;;一種木馬電路的實(shí)現(xiàn)與特征分析[J];微電子學(xué)與計(jì)算機(jī);2012年10期

5 鄒程;張鵬;鄧高明;吳恒旭;;基于功率旁路泄露的硬件木馬設(shè)計(jì)[J];計(jì)算機(jī)工程;2011年11期

6 張鵬;鄒程;鄧高明;陳開(kāi)顏;;基于電磁泄漏相關(guān)性分析的硬件木馬設(shè)計(jì)[J];華中科技大學(xué)學(xué)報(bào)(自然科學(xué)版);2010年10期

7 陳開(kāi)顏;趙強(qiáng);張鵬;周開(kāi)民;;集成電路芯片信息泄漏旁路分析模型[J];微計(jì)算機(jī)信息;2006年16期

相關(guān)博士學(xué)位論文 前1條

1 高洪博;指令誘發(fā)型硬件木馬檢測(cè)技術(shù)研究[D];解放軍信息工程大學(xué);2013年

相關(guān)碩士學(xué)位論文 前1條

1 房磊;基于門級(jí)網(wǎng)表的硬件木馬檢測(cè)技術(shù)研究[D];電子科技大學(xué);2014年

，

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