【摘要】：隨著網(wǎng)絡(luò)技術(shù)和硬件制造技術(shù)的迅猛發(fā)展,系統(tǒng)間的數(shù)據(jù)傳輸量快速增加,導(dǎo)致傳輸接口的數(shù)據(jù)傳輸速率成為了阻礙系統(tǒng)性能提升的關(guān)鍵因素。并行傳輸技術(shù)抗干擾能力弱,易產(chǎn)生串?dāng)_、時(shí)鐘偏斜等現(xiàn)象,導(dǎo)致其數(shù)據(jù)傳輸速率難以提升。而串行傳輸技術(shù)可以有效解決這些問題使傳輸速率達(dá)到更高水平,再加上端口少、功耗低等優(yōu)點(diǎn),串行鏈接技術(shù)(SerDes)受到越來越多的關(guān)注,逐漸成為數(shù)據(jù)傳輸?shù)闹髁骷夹g(shù)。本文通過對(duì)SerDes系統(tǒng)的研究,基于SMIC 0.13μm的CMOS工藝對(duì)SerDes接收端的信號(hào)丟失檢測(cè)電路和時(shí)鐘數(shù)據(jù)恢復(fù)電路進(jìn)行了研究設(shè)計(jì),并提出了一種抖動(dòng)容限的仿真驗(yàn)證方法。信號(hào)丟失檢測(cè)電路通過檢測(cè)輸入信號(hào)的差分?jǐn)[幅值來濾除嚴(yán)重失真的信號(hào)和耦合到輸入端的噪聲。本文設(shè)計(jì)的信號(hào)丟失檢測(cè)電路的閾值電壓可以跟隨輸入信號(hào)的共模電平變化,使檢測(cè)結(jié)果不受輸入信號(hào)共模電平的影響。時(shí)鐘數(shù)據(jù)恢復(fù)電路采用相位插值的結(jié)構(gòu)設(shè)計(jì),本文主要給出了相位跟蹤環(huán)路的電路設(shè)計(jì),包括采樣電路、相位檢測(cè)電路、表決器、插值控制電路和相位插值電路。其中,相位檢測(cè)電路采用Bang-Bang型的半速率相位檢測(cè)器,采樣時(shí)鐘頻率不超過數(shù)據(jù)傳輸速率,提高了數(shù)據(jù)傳輸速率。相位插值的方法是先將全周期分為8個(gè)相位區(qū)間,然后在時(shí)鐘所在的相位區(qū)間內(nèi)對(duì)時(shí)鐘相位進(jìn)行調(diào)節(jié)。該方法減小了插值步長(zhǎng),有利于準(zhǔn)確調(diào)節(jié)時(shí)鐘相位。本文還提出了一種抖動(dòng)容限的仿真驗(yàn)證方法,通過VerilogA語言產(chǎn)生帶抖動(dòng)的偽隨機(jī)數(shù)據(jù)作為測(cè)試信號(hào),通過Python腳本判斷仿真輸出信號(hào)是否出錯(cuò)。該方法在芯片設(shè)計(jì)階段對(duì)抖動(dòng)容限進(jìn)行仿真驗(yàn)證,有效的降低了流片風(fēng)險(xiǎn)。抖動(dòng)容限仿真結(jié)果表明,當(dāng)抖動(dòng)頻率在0.1MHz到10MHz之間時(shí),抖動(dòng)容限為0.61UI。在SerDes電路設(shè)計(jì)完成后,完成該芯片的版圖設(shè)計(jì)并將該芯片流片,然后對(duì)流片后的SerDse芯片進(jìn)行測(cè)試。SerDes芯片的版圖面積為2363×2422μm。測(cè)試結(jié)果表明該芯片工作正確,數(shù)據(jù)傳輸速率可達(dá)到2.5Gbps。
[Abstract]:With the rapid development of the network technology and hardware manufacturing technology, the data transmission rate among the systems is rapidly increased, resulting in the data transmission rate of the transmission interface becoming the key factor to hinder the performance of the system. The anti-interference ability of parallel transmission technology is weak, it is easy to generate cross-talk, clock skew, and so on, which causes the data transmission rate to be difficult to increase. The serial transmission technology can effectively solve these problems, so that the transmission rate can reach a higher level, and the serial link technology (SerDes) is more and more concerned and gradually becomes the mainstream technology of data transmission. Based on the research of SerDes system, the signal loss detection circuit and clock data recovery circuit of SerDes receiving end are designed based on the CMOS process of the SMIC 0.13. m u.m, and a method of simulation and verification of the jitter tolerance is proposed. The signal loss detection circuit filters out the signal of the severe distortion and the noise coupled to the input terminal by detecting the differential swing amplitude of the input signal. The threshold voltage of the signal loss detection circuit designed in this paper can follow the common-mode level change of the input signal, so that the detection result is not affected by the common-mode level of the input signal. The clock data recovery circuit adopts the structure design of phase interpolation, and the circuit design of the phase tracking loop is mainly given in this paper, including the sampling circuit, the phase detection circuit, the voter, the interpolation control circuit and the phase interpolation circuit. The phase detection circuit adopts the half-rate phase detector of the Bang-Bang type, the sampling clock frequency does not exceed the data transmission rate, and the data transmission rate is improved. The phase interpolation method comprises the following steps of: firstly, dividing the full period into 8 phase sections, and then adjusting the clock phase in the phase section where the clock is located. The method reduces the interpolation step size and is beneficial to the accurate adjustment of the clock phase. In this paper, a simulation and verification method for jitter tolerance is presented, and the pseudo-random data with jitter is generated as a test signal through Verilog language, and the error of the simulation output signal is judged by the Python script. In that method, the jitter tolerance is simulated and verified at the design stage of the chip, and the risk of the flow sheet is effectively reduced. The jitter tolerance simulation results show that the jitter margin is 0.61 UI when the jitter frequency is between 0.1 MHz and 10 MHz. After the SerDes circuit design is completed, the layout of the chip is completed and the chip flow is completed, and then the SerDes chip after the convection chip is tested. The serial area of the SerDes chip is 2363-2422. m u.m. The test results show that the chip is working correctly and the data transmission rate can reach 2.5 Gbps.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN402

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