【摘要】：小數(shù)型頻率合成器具有快速鎖定、高頻率分辨率以及低相位噪聲等方面的優(yōu)勢,在無線射頻通信芯片中得到了廣泛的應用。小數(shù)分頻器作為環(huán)路中的核心模塊之一,完成可編程且連續(xù)變化的分頻功能,是實現(xiàn)高性能小數(shù)型頻率合成器的前提和關(guān)鍵。論文的主要工作是設計一款基于△∑調(diào)制技術(shù)的小數(shù)分頻器。論文首先綜述了小數(shù)分頻技術(shù)的發(fā)展和研究現(xiàn)狀,從系統(tǒng)上分析了小數(shù)分頻的基本原理,總結(jié)了△∑調(diào)制器的性能優(yōu)化技術(shù)。為了評估系統(tǒng)環(huán)路中小數(shù)分頻器對總輸出相位噪聲的貢獻,建立了小數(shù)分頻器的噪聲模型。針對△∑調(diào)制器的設計,采用Simulink工具對△∑調(diào)制器進行建模分析,確定了△∑調(diào)制器的基本結(jié)構(gòu)和階數(shù),提出一種HK-MASH結(jié)構(gòu)和嵌套的混合基調(diào)制器相結(jié)合的設計方案,改善了輸出頻譜性能的同時消除了有限字長效應引入的頻率誤差。針對多模可編程分頻器的設計,采用SCL結(jié)構(gòu)與TSPC結(jié)構(gòu)相結(jié)合的方式實現(xiàn)分頻器功耗的降低,最后根據(jù)指標要求采用分頻比擴展技術(shù)設計了一款具有0.5分頻步長,分頻比的范圍達到32-127.5的多�？删幊谭诸l器。論文基于SMIC 0.18μmCMOS工藝,完成了小數(shù)分頻器的原理圖及版圖設計,并進行了仿真驗證。后仿真結(jié)果表明頻率合成器的鎖定時間小于10μs,其中小數(shù)分頻器的工作頻率范圍達到1.5GHz-2.8GHz,頻率分辨率為25Hz,全頻段內(nèi)相位噪聲優(yōu)于-135dBc/Hz@10KHz,1.8V的電源電壓下消耗的電流小于2.4mA,達到了設計要求。
[Abstract]:Decimal frequency synthesizer has been widely used in radio frequency communication chips because of its advantages of fast locking, high frequency resolution and low phase noise. As one of the core modules in the loop, the decimal frequency divider completes the programmable and continuous frequency division function, which is the premise and key to realize the high performance decimal frequency synthesizer. The main work of this paper is to design a decimal frequency divider based on Sigma modulation technology. In this paper, the development and research status of decimal frequency division technology are reviewed, the basic principle of decimal frequency division is analyzed systematically, and the performance optimization technology of Sigma modulator is summarized. In order to evaluate the contribution of the system loop decimal divider to the total output phase noise, the noise model of the decimal divider is established. Aiming at the design of Sigma modulator, the Simulink tool is used to model and analyze the Sigma modulator, the basic structure and order of Sigma modulator are determined, and a design scheme combining HK-MASH structure with nesting hybrid tuner is proposed. The output spectrum performance is improved and the frequency error introduced by the finite word length effect is eliminated. Aiming at the design of multimode programmable frequency divider, the power consumption of frequency divider is reduced by combining SCL structure with TSPC structure. Finally, a frequency division step length is designed by using frequency division ratio expansion technology according to the requirements of the index. A multimode programmable frequency divider with a frequency division ratio of 32 鈮，

本文編號：2494674