發(fā)布時(shí)間：2019-06-06 18:40

【摘要】：時(shí)間數(shù)字轉(zhuǎn)換(Time-to-Digital Converter, TDC)電路用于時(shí)間測(cè)量,將兩個(gè)異步信號(hào)所定義的持續(xù)時(shí)間間隔轉(zhuǎn)化為數(shù)字量輸出。TDC電路常用于實(shí)現(xiàn)一定動(dòng)態(tài)范圍內(nèi)的精密時(shí)間測(cè)量,在光子或粒子飛行時(shí)間檢測(cè)、脈沖信號(hào)持續(xù)時(shí)間檢測(cè)等各類系統(tǒng)中獲得了廣泛應(yīng)用,有力支撐了紅外傳感檢測(cè)、溫度檢測(cè)技術(shù)的發(fā)展。單模式TDC電路只有一種時(shí)間量化基本單位,無法兼顧高精度與寬量程的共同需求。因此,為了突破測(cè)量精度提高與量程范圍擴(kuò)展的相互制約關(guān)系,TDC必須依靠大小不同的量化單位TDC之間的配合,構(gòu)成多段式TDC,有效提高時(shí)間檢測(cè)的動(dòng)態(tài)范圍,提升檢測(cè)精度。本文提出的三段式TDC是在經(jīng)典兩段式TDC基礎(chǔ)上改進(jìn)得到：高段LFSR計(jì)數(shù)式TDC保持不變,實(shí)現(xiàn)所需的寬量程檢測(cè);同時(shí)將延遲式TDC的控制電壓改進(jìn)為DLL控制提供,提高中段TDC的性能水平,并在此基礎(chǔ)上進(jìn)一步引入游標(biāo)細(xì)分辨TDC,突破數(shù)字門電路最小延遲下限,實(shí)現(xiàn)高精度量化。與其他三段式TDC結(jié)構(gòu)相比,本設(shè)計(jì)在精度上突破門延遲限制基礎(chǔ)上,高段位實(shí)現(xiàn)了寬動(dòng)態(tài)范圍的量程擴(kuò)展,實(shí)現(xiàn)了兼顧精度和寬量程的共同需求。除此以外,本設(shè)計(jì)基于Dual-DLL架構(gòu),產(chǎn)生的壓控電壓穩(wěn)定性明顯優(yōu)于開環(huán)補(bǔ)充結(jié)構(gòu),在抑制環(huán)振頻率的相位噪聲或時(shí)鐘抖動(dòng)方面具有明顯優(yōu)勢(shì)。本論文設(shè)計(jì)的高精度與寬量程三段式TDC電路,在維持原有量程不變的條件下,其時(shí)間檢測(cè)分辨率突破了工藝決定的門延遲時(shí)間限制。本設(shè)計(jì)采用TSMC 0.35μm標(biāo)準(zhǔn)工藝,通過Cadence EDA工具驗(yàn)證,完成了整個(gè)電路前仿、版圖與后仿及流片驗(yàn)證。測(cè)試結(jié)果顯示,在40MHz輸入時(shí)鐘條件下,15bit三段式TDC測(cè)試量程可達(dá)4gs,同時(shí)轉(zhuǎn)換精度可限制在0.25ns以內(nèi),溫度-40℃～100℃時(shí)功能正常,滿足設(shè)計(jì)要求。
[Abstract]:Time digital conversion (Time-to-Digital Converter, TDC) circuit is used for time measurement, converting the duration interval defined by two asynchronous signals into digital output. TDC circuits are often used to realize precise time measurement in a certain dynamic range. It has been widely used in photonic or particle flight time detection, pulse signal duration detection and other systems, which strongly supports the development of infrared sensing detection and temperature detection technology. Single mode TDC circuits have only one basic unit of time quantification, which can not take into account the common needs of high precision and wide range. Therefore, in order to break through the mutual restriction between the improvement of measurement accuracy and the expansion of range, TDC must rely on the cooperation between quantitative units of different sizes to form a multi-segment TDC, to effectively improve the dynamic range of time detection and improve the detection accuracy. The three-stage TDC proposed in this paper is improved on the basis of the classical two-stage TDC: the high-segment LFSR counting TDC remains unchanged and the required wide range detection is realized; At the same time, the control voltage of delayed TDC is improved for DLL control, and the performance level of middle TDC is improved. on this basis, Vernier fine resolution TDC, is further introduced to break through the minimum delay lower limit of digital gate circuit to realize high precision quantification. Compared with other three-stage TDC structures, on the basis of breaking through the limitation of gate delay in precision, the high segment bit realizes the range expansion of wide dynamic range and realizes the common demand of taking into account the accuracy and wide range. In addition, based on Dual-DLL architecture, the voltage-controlled voltage stability of this design is obviously better than that of open-loop supplementary structure, and it has obvious advantages in suppressing the phase noise or clock jitter of ring vibration frequency. In this paper, the high precision and wide range three-stage TDC circuit is designed, and its time detection resolution breaks through the gate delay time limit determined by the process under the condition that the original range is unchanged. The design adopts TSMC 0.35 渭 m standard process and is verified by Cadence EDA tool. The whole circuit is verified by front imitation, layout, rear imitation and flow chip verification. The test results show that under the condition of 40MHz input clock, the test range of 15bit three-stage TDC can reach 4 GS, and the conversion accuracy can be limited to 0.25ns. The function is normal at-40 鈩，

本文編號(hào)：2494514