高速高精度流水線ADC設(shè)計(jì)與研究
發(fā)布時(shí)間：2019-05-26 21:33
【摘要】：模數(shù)轉(zhuǎn)換器廣泛應(yīng)用在無線通信中,就當(dāng)前的發(fā)展趨勢(shì)來看,社會(huì)對(duì)于高性能的ADC提出了更大的需求,高速高精度的應(yīng)用變得越來越普遍以及重要。更有甚者希望設(shè)計(jì)一種RF ADC取代傳統(tǒng)的前端接收網(wǎng)絡(luò),直接采樣射頻信號(hào),這從目前的發(fā)展來看并不是神話。工藝的進(jìn)步固然是件好事,數(shù)字處理芯片可以以更快更低的功耗完成計(jì)算存儲(chǔ)等任務(wù),可是高性能模擬電路的設(shè)計(jì)卻遇到了很大挑戰(zhàn),加上模擬電路的性能需要以功耗面積為代價(jià),應(yīng)用環(huán)境受到限制。目前的ADC依靠強(qiáng)大的數(shù)字校準(zhǔn)來輔助完成轉(zhuǎn)換任務(wù),是大勢(shì)所趨。本篇文章通過理論分析和仿真驗(yàn)證,針對(duì)流水線ADC前兩級(jí)電路的設(shè)計(jì)優(yōu)化,實(shí)現(xiàn)16bit、100M的高速高精度流水線ADC,并嘗試在無采樣保持結(jié)構(gòu)情況下實(shí)現(xiàn)雙通道時(shí)間交疊流水線模數(shù)轉(zhuǎn)換器的可行性。主要從以下四個(gè)方面討論分析:(1)系統(tǒng)結(jié)構(gòu)方面。采用一種低功耗的SHA-less結(jié)構(gòu),與傳統(tǒng)采樣保持結(jié)構(gòu)相比,節(jié)省了功耗的同時(shí)又貢獻(xiàn)較少的噪聲,并分析提出辦法解決新架構(gòu)會(huì)出現(xiàn)的問題。針對(duì)噪聲和功耗,首先分析誤差主要來源,以模塊為單位逐個(gè)分析并根據(jù)性能指標(biāo)推算基礎(chǔ)模塊所需實(shí)現(xiàn)的性能,最后提出一種噪聲功耗的分析方法。(2)模擬電路方面。設(shè)計(jì)了高性能的bootstrapped采樣開關(guān)、運(yùn)算放大器和動(dòng)態(tài)比較器,并創(chuàng)新提出了一種低抖動(dòng)的時(shí)鐘驅(qū)動(dòng)器,該模塊可以調(diào)整輸入時(shí)鐘的占空比至50%。運(yùn)放結(jié)構(gòu)的選擇中通過各自優(yōu)缺點(diǎn)的分析后決定使用兩級(jí)米勒補(bǔ)償結(jié)構(gòu),并采用了gain-boosting增益提升技術(shù)。比較器方面進(jìn)行微小改進(jìn)使之能有更快的響應(yīng)速度。低抖動(dòng)的時(shí)鐘驅(qū)動(dòng)器為了滿足高速的應(yīng)用場(chǎng)合,優(yōu)化clock jitter,同時(shí)在后面添加純數(shù)字的占空比穩(wěn)定電路,具有極低的建立時(shí)間,用來提升時(shí)間裕度,保證ADC有更好性能和可靠性。(3)數(shù)字校準(zhǔn)方面。利用Matlab建模仿真,通過分析并建立誤差模型實(shí)現(xiàn)典型的dithering技術(shù)對(duì)于流水線ADC第一級(jí)的增益誤差和電容不匹配的校準(zhǔn)。(4)嘗試采用雙通道的時(shí)間交疊技術(shù)進(jìn)行提速,對(duì)于無采樣保持情況下的雙通道情況進(jìn)行誤差分析。通過建模仿真驗(yàn)證其可行性。最終的電路仿真顯示單通道流水線ADC可以完成100M的采樣率、16比特的轉(zhuǎn)換工作,并且結(jié)果良好,低頻輸入時(shí)SNDR為76.8d B,SFDR為100d B;高頻輸入時(shí)SNDR為75.7d B,SFDR為97d B。雙通道實(shí)現(xiàn)16比特200M的性能,低頻信號(hào)輸入時(shí)SNDR為76.7d B,SFDR為100d B;高頻輸入時(shí)SNDR為75.5d B,SFDR為88d B。
[Abstract]:Analog-to-digital converter (ADC) is widely used in wireless communication. According to the current development trend, the society has put forward greater demand for high-performance ADC, and the application of high-speed and high-precision has become more and more common and important. What's more, it is not a myth to design a RF ADC to replace the traditional front-end receiving network and directly sample RF signals. Of course, the progress of the process is a good thing. The digital processing chip can complete the tasks of computing and storage with faster and lower power consumption, but the design of high performance analog circuit has encountered great challenges. In addition, the performance of analog circuits needs to be at the expense of power consumption area, and the application environment is limited. At present, ADC relies on powerful digital calibration to assist in the completion of conversion tasks, which is the general trend. In this paper, through theoretical analysis and simulation verification, the design optimization of the first two stages of pipelined ADC is carried out, and the high speed and high precision pipelined ADC, of 16bit100m is realized. The feasibility of realizing dual-channel time overlapping pipelined analog-to-digital converter without sampling and holding structure is tried. Mainly from the following four aspects of discussion and analysis: (1) the system structure. Compared with the traditional sampling and holding structure, a low power consumption SHA-less structure is adopted, which saves power consumption and contributes less noise, and analyzes and proposes a method to solve the problems of the new architecture. For noise and power consumption, the main sources of error are analyzed, and the performance of the basic module is analyzed one by one according to the performance index. Finally, an analysis method of noise power consumption is proposed. (2) Analog circuit. A high performance bootstrapped sampling switch, operational amplifier and dynamic comparator are designed, and a low jitter clock driver is proposed, which can adjust the duty cycle of the input clock to 50%. Through the analysis of their advantages and disadvantages, the two-stage Hans Muller compensation structure is decided to be used in the selection of operational amplifier structure, and the gain-boosting gain lifting technology is adopted. Minor improvements have been made in the comparator to enable it to respond faster. In order to meet the needs of high speed applications, the low jitter clock driver optimizes the clock jitter, and adds a pure digital duty cycle stable circuit to the rear, which has a very low setup time and is used to improve the time margin. Ensure better performance and reliability of ADC. (3) Digital calibration. By using Matlab modeling and simulation, the typical dithering technology is analyzed and established to calibrate the gain error and capacitance mismatch in the first stage of pipeline ADC. (4) the dual-channel time overlap technique is used to speed up the calibration of the gain error and capacitance mismatch in the first stage of pipeline ADC. The error analysis of the two-channel case without sampling and holding is carried out. Its feasibility is verified by building and imitating. The final circuit simulation shows that the single-channel pipelined ADC can complete 100m sampling rate and 16-bit conversion, and the results are good. SNDR is 76.8dB and SFDR is 100dB at low frequency input, and SNDR is 75.7 d B at high frequency input and 97dB at high frequency input. The performance of 16-bit 200m is achieved in two channels. SNDR is 76.7d B and SFDR is 100dB in low frequency signal input, SNDR is 75.5 d B in high frequency input and 88dB in high frequency input.
【學(xué)位授予單位】：上海交通大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN792
本文編號(hào)：2485651
[Abstract]:Analog-to-digital converter (ADC) is widely used in wireless communication. According to the current development trend, the society has put forward greater demand for high-performance ADC, and the application of high-speed and high-precision has become more and more common and important. What's more, it is not a myth to design a RF ADC to replace the traditional front-end receiving network and directly sample RF signals. Of course, the progress of the process is a good thing. The digital processing chip can complete the tasks of computing and storage with faster and lower power consumption, but the design of high performance analog circuit has encountered great challenges. In addition, the performance of analog circuits needs to be at the expense of power consumption area, and the application environment is limited. At present, ADC relies on powerful digital calibration to assist in the completion of conversion tasks, which is the general trend. In this paper, through theoretical analysis and simulation verification, the design optimization of the first two stages of pipelined ADC is carried out, and the high speed and high precision pipelined ADC, of 16bit100m is realized. The feasibility of realizing dual-channel time overlapping pipelined analog-to-digital converter without sampling and holding structure is tried. Mainly from the following four aspects of discussion and analysis: (1) the system structure. Compared with the traditional sampling and holding structure, a low power consumption SHA-less structure is adopted, which saves power consumption and contributes less noise, and analyzes and proposes a method to solve the problems of the new architecture. For noise and power consumption, the main sources of error are analyzed, and the performance of the basic module is analyzed one by one according to the performance index. Finally, an analysis method of noise power consumption is proposed. (2) Analog circuit. A high performance bootstrapped sampling switch, operational amplifier and dynamic comparator are designed, and a low jitter clock driver is proposed, which can adjust the duty cycle of the input clock to 50%. Through the analysis of their advantages and disadvantages, the two-stage Hans Muller compensation structure is decided to be used in the selection of operational amplifier structure, and the gain-boosting gain lifting technology is adopted. Minor improvements have been made in the comparator to enable it to respond faster. In order to meet the needs of high speed applications, the low jitter clock driver optimizes the clock jitter, and adds a pure digital duty cycle stable circuit to the rear, which has a very low setup time and is used to improve the time margin. Ensure better performance and reliability of ADC. (3) Digital calibration. By using Matlab modeling and simulation, the typical dithering technology is analyzed and established to calibrate the gain error and capacitance mismatch in the first stage of pipeline ADC. (4) the dual-channel time overlap technique is used to speed up the calibration of the gain error and capacitance mismatch in the first stage of pipeline ADC. The error analysis of the two-channel case without sampling and holding is carried out. Its feasibility is verified by building and imitating. The final circuit simulation shows that the single-channel pipelined ADC can complete 100m sampling rate and 16-bit conversion, and the results are good. SNDR is 76.8dB and SFDR is 100dB at low frequency input, and SNDR is 75.7 d B at high frequency input and 97dB at high frequency input. The performance of 16-bit 200m is achieved in two channels. SNDR is 76.7d B and SFDR is 100dB in low frequency signal input, SNDR is 75.5 d B in high frequency input and 88dB in high frequency input.
【學(xué)位授予單位】：上海交通大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN792
【參考文獻(xiàn)】
相關(guān)碩士學(xué)位論文 前1條
1 汪月花;基于功耗和線性度優(yōu)化的Pipeline ADC系統(tǒng)建模[D];電子科技大學(xué);2008年
，本文編號(hào)：2485651
本文鏈接：http://sikaile.net/kejilunwen/dianzigongchenglunwen/2485651.html
最近更新
教材專著
