基于GTX的JESD204B數(shù)據(jù)接收接口研究與實(shí)現(xiàn)
發(fā)布時(shí)間：2019-03-31 09:48
【摘要】：高速數(shù)據(jù)采集在無線通信、醫(yī)療影像、高速儀器儀表和雷達(dá)等領(lǐng)域占有非常重要的地位。隨著數(shù)據(jù)轉(zhuǎn)換器采集速率的提高,與采集數(shù)據(jù)串行傳輸方式相比,傳統(tǒng)并行傳輸方式在降低碼間同步難度、減小碼間串?dāng)_、降低布線復(fù)雜度和減小資源消耗等方面漸漸暴露其自身的弱點(diǎn)。當(dāng)前已有多款集成有JESD204B發(fā)送接口的AD芯片問世。JESD204B數(shù)據(jù)接收接口在這種條件下應(yīng)運(yùn)而生。國外雖提供有JESD204B接收接口的商業(yè)IP核,但該IP核需要收費(fèi)。更重要的是,第三方提供的IP核關(guān)鍵部分的邏輯電路以“黑盒”的方式提供,使用者并不了解其中的細(xì)節(jié)。在國防軍工領(lǐng)域直接使用這些“黑盒”電路給國防安全留下了隱患。針對上述情況,本文在研究JESD204B接收接口的原理及結(jié)構(gòu)的基礎(chǔ)上,探索JESD204B接收接口在FPGA上的實(shí)現(xiàn)。該實(shí)現(xiàn)分兩大部分展開:首先在研究JESD204B接收接口結(jié)構(gòu)和功能的基礎(chǔ)上進(jìn)行總體設(shè)計(jì),分析采用GTX高速收發(fā)器實(shí)現(xiàn)JESD204B接收接口物理層的可行性,研究鏈路層實(shí)現(xiàn)方案,確定傳輸層數(shù)據(jù)格式并給出傳輸層數(shù)據(jù)提取方案;接著分析實(shí)現(xiàn)JESD204B接收接口的關(guān)鍵問題及解決思路。為了驗(yàn)證設(shè)計(jì)的JESD204B接收接口的性能,對實(shí)現(xiàn)的JESD204B接收接口進(jìn)行了仿真測試和板級實(shí)測。仿真結(jié)果表明:1)實(shí)現(xiàn)的JESD204B接收接口邏輯功能正確,2)Vivado給出的時(shí)序分析報(bào)告滿足電路工作頻率要求。板級實(shí)測結(jié)果表明實(shí)現(xiàn)的JESD204B接收接口功能正確,工作穩(wěn)定。
[Abstract]:High-speed data acquisition plays an important role in wireless communication, medical imaging, high-speed instrument and radar. With the increase of the acquisition rate of the data converter, compared with the serial transmission mode of the acquisition data, the traditional parallel transmission mode reduces the difficulty of inter-symbol synchronization and the inter-symbol crosstalk. Reduce the complexity of routing and reduce the consumption of resources and other aspects gradually exposed its own weaknesses. At present, there are many AD chips integrated with JESD204B sending interface, and the JESD204B data receiving interface comes into being under this condition. Although foreign countries provide a commercial IP core with a JESD204B receiver interface, the IP core requires a fee. More importantly, the logic circuit of the IP core provided by the third party is provided in a "black box" manner, and the user does not know the details of it. The direct use of these "black box" circuits in the field of national defense and military industry leaves a hidden danger to the security of national defense. In view of the above situation, on the basis of studying the principle and structure of the JESD204B receiving interface, this paper explores the realization of the JESD204B receiving interface on the FPGA. The implementation is divided into two parts: firstly, based on the research of the structure and function of JESD204B receiving interface, the feasibility of using GTX high-speed transceiver to realize the physical layer of JESD204B receiver interface is analyzed, and the implementation scheme of link layer is studied. The data format of the transport layer is determined and the data extraction scheme of the transport layer is given. Then the key problems and solutions of JESD204B receiver interface are analyzed. In order to verify the performance of the designed JESD204B receiver interface, the simulation test and board-level measurement of the implemented JESD204B receiver interface are carried out. The simulation results show that: 1) the logic function of the JESD204B receiver interface is correct; 2) the timing analysis report given by Vivado meets the requirement of the circuit working frequency. The experimental results at the board level show that the function of the JESD204B receiver interface is correct and the operation is stable.
【學(xué)位授予單位】：國防科學(xué)技術(shù)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN79
本文編號：2450797
[Abstract]:High-speed data acquisition plays an important role in wireless communication, medical imaging, high-speed instrument and radar. With the increase of the acquisition rate of the data converter, compared with the serial transmission mode of the acquisition data, the traditional parallel transmission mode reduces the difficulty of inter-symbol synchronization and the inter-symbol crosstalk. Reduce the complexity of routing and reduce the consumption of resources and other aspects gradually exposed its own weaknesses. At present, there are many AD chips integrated with JESD204B sending interface, and the JESD204B data receiving interface comes into being under this condition. Although foreign countries provide a commercial IP core with a JESD204B receiver interface, the IP core requires a fee. More importantly, the logic circuit of the IP core provided by the third party is provided in a "black box" manner, and the user does not know the details of it. The direct use of these "black box" circuits in the field of national defense and military industry leaves a hidden danger to the security of national defense. In view of the above situation, on the basis of studying the principle and structure of the JESD204B receiving interface, this paper explores the realization of the JESD204B receiving interface on the FPGA. The implementation is divided into two parts: firstly, based on the research of the structure and function of JESD204B receiving interface, the feasibility of using GTX high-speed transceiver to realize the physical layer of JESD204B receiver interface is analyzed, and the implementation scheme of link layer is studied. The data format of the transport layer is determined and the data extraction scheme of the transport layer is given. Then the key problems and solutions of JESD204B receiver interface are analyzed. In order to verify the performance of the designed JESD204B receiver interface, the simulation test and board-level measurement of the implemented JESD204B receiver interface are carried out. The simulation results show that: 1) the logic function of the JESD204B receiver interface is correct; 2) the timing analysis report given by Vivado meets the requirement of the circuit working frequency. The experimental results at the board level show that the function of the JESD204B receiver interface is correct and the operation is stable.
【學(xué)位授予單位】：國防科學(xué)技術(shù)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN79
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