基于隨機化聚類算法的掃描時鐘分組方法
發(fā)布時間：2019-03-20 11:20
【摘要】：目前,基于IP(Intellectual Property)復(fù)用的片上系統(tǒng)設(shè)計方法使得專用集成電路(ASIC,Application Specific Integrated Circuit)的設(shè)計效率大幅提高。但這種方法也帶來了新的挑戰(zhàn),高性能集成電路的可測性設(shè)計(DFT,Design For Testability)就是其中最嚴峻的部分。本課題主要是實現(xiàn)了一款含有同步與異步時鐘域的大規(guī)模數(shù)字基帶芯片的ATPG(Automatic Test Pattern Generation,自動測試圖形生成)時鐘結(jié)構(gòu)優(yōu)化設(shè)計。對大規(guī)模的集成電路測試平臺,因其電路復(fù)雜性高,要達到非常高的故障覆蓋率(fault coverage)是非常困難的。如何在保證故障覆蓋率的同時減少測試向量數(shù)量,成為減少測試成本的研究熱點。本文以數(shù)字基帶芯片的測試向量生成時的時鐘結(jié)構(gòu)為研究對象,以提高故障覆蓋率和減少測試向量數(shù)量為主要目標(biāo),設(shè)計了隨機化聚類算法應(yīng)用于生成掃描時鐘結(jié)構(gòu),并提出改進型的錯位捕獲(staggered LOC)技術(shù)產(chǎn)生測試向量。本文的主要研究內(nèi)容和所取得的成果如下:1.在諸聚類算法中,層次聚類算法具有速度快,算法簡單的特點,但是其精度較低。本文在層次聚類算法中引入隨機化步驟,使算法運行過程帶有隨機成分,并在多次運行后挑選優(yōu)化的結(jié)果,彌補了層次聚類算法精確度不足的缺點。使之成為適合對含有同步與異步時鐘域的大規(guī)模芯片進行時鐘分組的算法。2.在stuck-at測試模式下,用隨機化聚類算法對時鐘域進行分組,得到優(yōu)化的掃描時鐘結(jié)構(gòu),可以減少跨時鐘域傳播路徑的數(shù)量,提高故障覆蓋率。3.在延時測試(delay test)模式下,通過隨機化聚類算法對時鐘域進行分組,將互相之間沒有跨時鐘域傳輸路徑的異步時鐘域劃分成一組。在同一捕獲窗口(capture window)內(nèi)利用并行捕獲(simultaneous Launch-on-Capture)與改進型錯位捕獲(staggered capture)技術(shù),對時鐘域組進行組內(nèi)并行,組間串行的測試捕獲(launch-capture)方法。可以較大程度減少測試向量數(shù)量,縮短機臺測試時間。
[Abstract]:At present, the design efficiency of application-specific integrated circuit (ASIC,Application Specific Integrated Circuit) is greatly improved by the method of system-on-a-chip design based on IP (Intellectual Property) multiplexing. But this approach also presents new challenges, and the testability design of high-performance integrated circuits (DFT,Design For Testability) is one of the toughest. In this paper, a large-scale digital baseband chip with synchronous and asynchronous clock domain (ATPG (Automatic Test Pattern Generation, automatic test pattern generation) clock structure optimization design is implemented. For large scale integrated circuit test platform, it is very difficult to achieve very high fault coverage (fault coverage) because of its high circuit complexity. How to reduce the number of test vectors while ensuring fault coverage has become a hot topic to reduce the cost of testing. Taking the clock structure of test vector generation in digital baseband chip as the research object, in order to improve the fault coverage and reduce the number of test vectors as the main goal, a randomized clustering algorithm is designed and applied to generate scan clock structure. An improved dislocation capture (staggered LOC) technique is proposed to generate test vectors. The main contents and achievements of this paper are as follows: 1. Among all clustering algorithms, hierarchical clustering algorithm has the characteristics of fast speed and simple algorithm, but its precision is low. In this paper, the randomization step is introduced into the hierarchical clustering algorithm to make the algorithm run with random components, and the optimization results are selected after many runs, which make up for the shortcomings of the lack of accuracy of the hierarchical clustering algorithm. To make it suitable for clock grouping on large-scale chips with synchronous and asynchronous clock domains. 2. In the stuck-at test mode, the random clustering algorithm is used to group the clock domain, and the optimized scan clock structure is obtained, which can reduce the number of propagation paths across the clock domain and improve the fault coverage. 3. In the delay test (delay test) mode, the asynchronous clock domain, which has no transmission path across the clock domain, is divided into a group by means of randomizing clustering algorithm. In the same acquisition window, parallel capture (simultaneous Launch-on-Capture) and improved dislocation capture (staggered capture) techniques are used to implement intra-group parallelism for clock domain groups and serial test capture (launch-capture) method for inter-group groups in the same acquisition window (capture window). It can greatly reduce the number of test vectors and shorten the test time.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN407
[Abstract]:At present, the design efficiency of application-specific integrated circuit (ASIC,Application Specific Integrated Circuit) is greatly improved by the method of system-on-a-chip design based on IP (Intellectual Property) multiplexing. But this approach also presents new challenges, and the testability design of high-performance integrated circuits (DFT,Design For Testability) is one of the toughest. In this paper, a large-scale digital baseband chip with synchronous and asynchronous clock domain (ATPG (Automatic Test Pattern Generation, automatic test pattern generation) clock structure optimization design is implemented. For large scale integrated circuit test platform, it is very difficult to achieve very high fault coverage (fault coverage) because of its high circuit complexity. How to reduce the number of test vectors while ensuring fault coverage has become a hot topic to reduce the cost of testing. Taking the clock structure of test vector generation in digital baseband chip as the research object, in order to improve the fault coverage and reduce the number of test vectors as the main goal, a randomized clustering algorithm is designed and applied to generate scan clock structure. An improved dislocation capture (staggered LOC) technique is proposed to generate test vectors. The main contents and achievements of this paper are as follows: 1. Among all clustering algorithms, hierarchical clustering algorithm has the characteristics of fast speed and simple algorithm, but its precision is low. In this paper, the randomization step is introduced into the hierarchical clustering algorithm to make the algorithm run with random components, and the optimization results are selected after many runs, which make up for the shortcomings of the lack of accuracy of the hierarchical clustering algorithm. To make it suitable for clock grouping on large-scale chips with synchronous and asynchronous clock domains. 2. In the stuck-at test mode, the random clustering algorithm is used to group the clock domain, and the optimized scan clock structure is obtained, which can reduce the number of propagation paths across the clock domain and improve the fault coverage. 3. In the delay test (delay test) mode, the asynchronous clock domain, which has no transmission path across the clock domain, is divided into a group by means of randomizing clustering algorithm. In the same acquisition window, parallel capture (simultaneous Launch-on-Capture) and improved dislocation capture (staggered capture) techniques are used to implement intra-group parallelism for clock domain groups and serial test capture (launch-capture) method for inter-group groups in the same acquisition window (capture window). It can greatly reduce the number of test vectors and shorten the test time.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN407
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1 王健波,曾成碧,苗虹;減小數(shù)字電路測試功耗的方法——測試向量排序法[J];四川大學(xué)學(xué)報(工程科學(xué)版);2000年06期
2 曾成碧,段述江,陳光，
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