【摘要】：隨著半導(dǎo)體技術(shù)的飛速發(fā)展,集成電路的集成度越來(lái)越來(lái)高,其性能不斷提升的同時(shí),其可靠性正面臨著巨大的挑戰(zhàn)。為確保其能在使用周期內(nèi)正常運(yùn)行,使得集成電路老化效應(yīng)成為可靠性問(wèn)題的關(guān)鍵。集成電路老化效應(yīng)會(huì)使組合電路延時(shí)增加,引起時(shí)序錯(cuò)誤,最終導(dǎo)致電路功能失效。因此針對(duì)集成電路老化效應(yīng)引起的時(shí)序錯(cuò)誤,需要尋找有效的測(cè)試與防護(hù)方法�；诖�,本文主要對(duì)集成電路老化在線預(yù)測(cè)與檢測(cè)技術(shù)進(jìn)行研究。本文首先介紹了集成電路老化效應(yīng)的機(jī)理,同步時(shí)序電路的時(shí)序約束,并逐步闡述兩者的聯(lián)系,從而清晰的說(shuō)明了集成電路老化如何引起時(shí)序錯(cuò)誤,也就是本文研究的核心問(wèn)題。然后,介紹了基于此問(wèn)題現(xiàn)有的兩種有效測(cè)試方法:集成電路老化在線預(yù)測(cè)技術(shù)與集成電路老化在線檢測(cè)技術(shù)。最后分別詳細(xì)的介紹了兩種技術(shù)下,所提的測(cè)試方法與測(cè)試結(jié)構(gòu)單元,分析了它們的原理,優(yōu)點(diǎn),缺點(diǎn)�；陬A(yù)測(cè)技術(shù),本文提出了一種用于容忍動(dòng)態(tài)頻率變化的穩(wěn)定性檢測(cè)器設(shè)計(jì)。通過(guò)原系統(tǒng)時(shí)鐘構(gòu)建新的監(jiān)測(cè)區(qū)間,利用新設(shè)計(jì)的穩(wěn)定性檢測(cè)器將組合電路違規(guī)跳變轉(zhuǎn)化成檢測(cè)脈沖,最后采集檢測(cè)脈沖從而發(fā)出報(bào)警信號(hào)。仿真結(jié)果表明,該方法可以容忍時(shí)鐘頻率變化,面積開(kāi)銷上具有一定的優(yōu)勢(shì),且將原來(lái)的兩個(gè)浮空節(jié)點(diǎn)轉(zhuǎn)化成一個(gè)節(jié)點(diǎn),提高了整個(gè)穩(wěn)定性檢測(cè)器的檢測(cè)能力。結(jié)合兩種測(cè)試技術(shù),本文提出了考慮預(yù)采樣的時(shí)序錯(cuò)誤檢測(cè)與自恢復(fù)方法。利用系統(tǒng)本身時(shí)鐘在時(shí)鐘有效沿前后構(gòu)建一個(gè)預(yù)采樣區(qū)間和一個(gè)檢測(cè)區(qū)間,并在預(yù)采樣區(qū)間內(nèi)提前捕獲輸入信號(hào),最后在檢測(cè)區(qū)間內(nèi)進(jìn)行時(shí)序錯(cuò)誤檢測(cè),如果檢測(cè)電路發(fā)出報(bào)警信號(hào),電路將會(huì)進(jìn)行自糾錯(cuò)。仿真結(jié)果表明,相比于其他的檢測(cè)結(jié)構(gòu),該結(jié)構(gòu)在檢測(cè)速度上平均提高了 3.6倍;同時(shí)不需要調(diào)整時(shí)序,電路就可以實(shí)現(xiàn)自糾錯(cuò)與自恢復(fù),且不會(huì)降低電路的工作性能。本文所提出的兩種測(cè)試方法,能夠很好的檢測(cè)集成電路老化引起的時(shí)序錯(cuò)誤,對(duì)于解決集成電路的可靠性問(wèn)題具有一定的價(jià)值。
[Abstract]:With the rapid development of semiconductor technology, the integration of integrated circuits becomes more and more high, and its reliability is facing great challenges while its performance is continuously improved. In order to ensure that the IC can operate normally in service cycle, the aging effect of IC becomes the key to reliability problem. The aging effect of the integrated circuit will increase the delay of the combined circuit, cause the timing error, and finally lead to the failure of the circuit function. Therefore, in view of the timing errors caused by the aging effect of integrated circuits, it is necessary to find effective testing and protection methods. Based on this, the on-line prediction and detection technology of IC aging is studied in this paper. This paper first introduces the mechanism of the aging effect of integrated circuits, the timing constraints of synchronous sequential circuits, and expounds the relationship between them step by step, so as to clearly explain how the aging of integrated circuits causes timing errors. That is, the core of this paper. Then, two effective testing methods are introduced: on-line prediction of IC aging and on-line testing of IC aging. Finally, the proposed test methods and test structure units are introduced in detail under the two technologies, and their principles, advantages and disadvantages are analyzed. Based on prediction technique, a design of stability detector for dynamic frequency change tolerance is proposed in this paper. A new monitoring interval is constructed by using the original system clock, and a new designed stability detector is used to transform the combination circuit violation jump into a detection pulse. Finally, the detection pulse is collected and an alarm signal is sent out. The simulation results show that the proposed method can tolerate the change of clock frequency and has some advantages in area overhead, and the original two floating nodes are transformed into one node, which improves the detection ability of the whole stability detector. Combined with two testing techniques, this paper presents a method of timing error detection and self-recovery considering pre-sampling. The clock of the system is used to construct a pre-sampling interval and a detection interval before and after the clock effectively, and the input signal is captured in advance in the pre-sampling interval. Finally, the timing error detection is carried out in the detection interval. If the detection circuit sends an alarm signal, the circuit will perform self-error correction. The simulation results show that, compared with other detection structures, the detection speed of this structure is increased 3.6 times on average, and the circuit can achieve self-error correction and self-recovery without adjusting the timing, and the performance of the circuit can not be reduced. The two testing methods proposed in this paper can well detect the timing errors caused by the aging of integrated circuits and have certain value in solving the reliability problems of integrated circuits.
【學(xué)位授予單位】：合肥工業(yè)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN407

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