NMOS器件熱載流子效應(yīng)研究
發(fā)布時間：2019-03-09 19:03
【摘要】：超大規(guī)模集成電路的迅速發(fā)展,迫切要求提高整個電路系統(tǒng)及單個器件的性能與可靠性,這是因為集成電路是由元器件組成的,單個器件的性能與質(zhì)量直接決定系統(tǒng)的可靠性。熱載流子效應(yīng)作為重要的可靠性問題之一,通過縱向與橫向的高強度電場能夠破壞器件氧化層的質(zhì)量,降低使用壽命,不僅會導(dǎo)致閾值電壓、最大跨導(dǎo)以及飽和漏電流等標(biāo)志器件可靠性的參數(shù)漂移,還會引起柵泄漏電流的增大,嚴(yán)重影響電路系統(tǒng)的穩(wěn)定性與可靠性,因而,對熱載流子效應(yīng)進(jìn)行深入的研究具有重要的意義。本論文針對NMOS器件中的熱載流子效應(yīng)以及HCI應(yīng)力導(dǎo)致的柵泄漏電流SILC的退化進(jìn)行了深入的探究。先從HCI效應(yīng)的本質(zhì)出發(fā),探討引起NMOSFET失效的HCI物理機制,闡述NMOSFET內(nèi)部熱載流子的產(chǎn)生方式與運動規(guī)律,重點介紹了有關(guān)HCI效應(yīng)的重要模型,經(jīng)典的物理模型包括襯底電流模型和幸運電子模型,指出這兩種模型分別從襯底電流及柵電流兩個方面來描述熱載流子的運動過程;其次給出有關(guān)探究NMOSFET熱載流子效應(yīng)的不同測試方法,針對Silvaco仿真軟件進(jìn)行了較為詳細(xì)的說明,指出該軟件對于研究NMOS器件熱載流子效應(yīng)的重要輔助作用。通過對柵氧厚度為4nm的NMOS器件進(jìn)行一系列實驗測試,結(jié)合仿真軟件的模擬結(jié)果,研究器件的溝道長度、溝道寬度、應(yīng)力條件等對襯底電流及柵電流的影響,由此確定導(dǎo)致器件熱載流子效應(yīng)最為嚴(yán)重的最壞HCI應(yīng)力條件,并研究了最壞應(yīng)力條件與結(jié)構(gòu)參數(shù)的關(guān)系,深入分析了溝道長度對最壞柵壓的影響以及導(dǎo)致應(yīng)力條件轉(zhuǎn)變的物理機制;通過間斷應(yīng)力實驗,研究了NMOS器件在熱載流子應(yīng)力下的參數(shù)退化,主要有閾值電壓正向漂移、最大跨導(dǎo)減小以及飽和漏電流降低等,并研究了HCI應(yīng)力作用下柵泄漏電流退化的機制,認(rèn)為造成SILC漂移的重要因素是柵氧化層中陷阱電荷的增加,并通過實驗證明了熱載流子效應(yīng)能夠引起NMOS器件的SILC隨應(yīng)力時間以指數(shù)規(guī)律增大,結(jié)合襯底電流模型與幸運電子模型,將SILC的漂移與閾值電壓、襯底電流峰值的漂移進(jìn)行對比分析,發(fā)現(xiàn)它們擬合成一條直線,這說明熱載流子效應(yīng)確實是導(dǎo)致NMOS器件SILC漂移的重要因素,與此同時也可以用HCI效應(yīng)過程中產(chǎn)生的柵泄漏電流來表征NMOSFET在HCI應(yīng)力下造成的損傷以及性能的退化。最后,從理論上指出采用間斷應(yīng)力方式進(jìn)行測試有可能會產(chǎn)生的實驗誤差,并設(shè)計了不間斷應(yīng)力實驗,將測試結(jié)果與間斷應(yīng)力進(jìn)行對比,發(fā)現(xiàn)確實存在少量的誤差,這說明在間斷應(yīng)力測試的過程中,測試時間內(nèi)器件性能的恢復(fù)是存在的,這也為研究HCI應(yīng)力下NMOS器件的損傷恢復(fù)提供了有效的思路與方法。
[Abstract]:With the rapid development of VLSI, it is urgent to improve the performance and reliability of the whole circuit system and single device. This is because the integrated circuit is composed of components, and the performance and quality of the single device directly determine the reliability of the system. Hot carrier effect, as one of the important reliability problems, can destroy the quality of oxide layer and reduce the service life through longitudinal and transverse high strength electric fields, which will not only lead to threshold voltage. The parameter drift of device reliability, such as maximum transconductance and saturation leakage current, will also cause the increase of gate leakage current, which will seriously affect the stability and reliability of the circuit system. It is of great significance to study the hot carrier effect in depth. The hot carrier effect in NMOS devices and the degradation of gate leakage current (SILC) caused by HCI stress are discussed in this paper. Starting from the essence of HCI effect, this paper discusses the physical mechanism of NMOSFET failure, expounds the mode of generation and movement of hot carriers in NMOSFET, and emphatically introduces the important models of HCI effect. The classical physical models include the substrate current model and the lucky electron model. It is pointed out that the two models describe the hot carrier motion from two aspects: the substrate current and the gate current. Secondly, different testing methods for exploring the hot carrier effect of NMOSFET are given, and the Silvaco simulation software is described in detail. It is pointed out that the software plays an important auxiliary role in studying the hot carrier effect of NMOS devices. The effects of channel length, channel width and stress condition on substrate current and gate current of NMOS devices with gate oxygen thickness of 4nm are studied by means of a series of experimental tests, combined with the simulation results of simulation software, and the effects of channel length, channel width and stress conditions on the substrate current and gate current are studied. The worst HCI stress condition which leads to the most serious hot carrier effect of the device is determined and the relationship between the worst stress condition and the structural parameters is studied. The influence of channel length on the worst gate voltage and the physical mechanism of stress condition transformation are analyzed. Through the discontinuous stress experiment, the parameter degradation of NMOS device under hot carrier stress is studied, such as the forward drift of threshold voltage, the decrease of maximum transconductance and the decrease of saturated leakage current, etc. The degradation mechanism of gate leakage current under HCI stress is studied. It is considered that the important factor causing SILC drift is the increase of trap charge in gate oxide. It is proved by experiments that the hot carrier effect can cause the SILC of NMOS devices to increase exponentially with the stress time. The drift and threshold voltage of SILC are combined with the substrate current model and lucky electron model. By comparing and analyzing the drift of the peak current of the substrate, it is found that they fit into a straight line, which indicates that the hot carrier effect is indeed an important factor leading to the SILC drift of the NMOS device. At the same time, the gate leakage current generated in the process of HCI effect can also be used to characterize the damage caused by NMOSFET under HCI stress and the degradation of its performance. Finally, it is pointed out theoretically that there may be experimental errors caused by discontinuous stress testing, and the uninterrupted stress experiment is designed. Comparing the measured results with the discontinuous stress, it is found that there are a few errors. This shows that the recovery of device performance during the test time exists in the process of discontinuous stress testing, which also provides an effective way to study the damage recovery of NMOS devices under HCI stress.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN386
本文編號：2437766
[Abstract]:With the rapid development of VLSI, it is urgent to improve the performance and reliability of the whole circuit system and single device. This is because the integrated circuit is composed of components, and the performance and quality of the single device directly determine the reliability of the system. Hot carrier effect, as one of the important reliability problems, can destroy the quality of oxide layer and reduce the service life through longitudinal and transverse high strength electric fields, which will not only lead to threshold voltage. The parameter drift of device reliability, such as maximum transconductance and saturation leakage current, will also cause the increase of gate leakage current, which will seriously affect the stability and reliability of the circuit system. It is of great significance to study the hot carrier effect in depth. The hot carrier effect in NMOS devices and the degradation of gate leakage current (SILC) caused by HCI stress are discussed in this paper. Starting from the essence of HCI effect, this paper discusses the physical mechanism of NMOSFET failure, expounds the mode of generation and movement of hot carriers in NMOSFET, and emphatically introduces the important models of HCI effect. The classical physical models include the substrate current model and the lucky electron model. It is pointed out that the two models describe the hot carrier motion from two aspects: the substrate current and the gate current. Secondly, different testing methods for exploring the hot carrier effect of NMOSFET are given, and the Silvaco simulation software is described in detail. It is pointed out that the software plays an important auxiliary role in studying the hot carrier effect of NMOS devices. The effects of channel length, channel width and stress condition on substrate current and gate current of NMOS devices with gate oxygen thickness of 4nm are studied by means of a series of experimental tests, combined with the simulation results of simulation software, and the effects of channel length, channel width and stress conditions on the substrate current and gate current are studied. The worst HCI stress condition which leads to the most serious hot carrier effect of the device is determined and the relationship between the worst stress condition and the structural parameters is studied. The influence of channel length on the worst gate voltage and the physical mechanism of stress condition transformation are analyzed. Through the discontinuous stress experiment, the parameter degradation of NMOS device under hot carrier stress is studied, such as the forward drift of threshold voltage, the decrease of maximum transconductance and the decrease of saturated leakage current, etc. The degradation mechanism of gate leakage current under HCI stress is studied. It is considered that the important factor causing SILC drift is the increase of trap charge in gate oxide. It is proved by experiments that the hot carrier effect can cause the SILC of NMOS devices to increase exponentially with the stress time. The drift and threshold voltage of SILC are combined with the substrate current model and lucky electron model. By comparing and analyzing the drift of the peak current of the substrate, it is found that they fit into a straight line, which indicates that the hot carrier effect is indeed an important factor leading to the SILC drift of the NMOS device. At the same time, the gate leakage current generated in the process of HCI effect can also be used to characterize the damage caused by NMOSFET under HCI stress and the degradation of its performance. Finally, it is pointed out theoretically that there may be experimental errors caused by discontinuous stress testing, and the uninterrupted stress experiment is designed. Comparing the measured results with the discontinuous stress, it is found that there are a few errors. This shows that the recovery of device performance during the test time exists in the process of discontinuous stress testing, which also provides an effective way to study the damage recovery of NMOS devices under HCI stress.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN386
【參考文獻(xiàn)】
相關(guān)期刊論文 前8條
1 朱筠;;利用SILVACO TCAD軟件改進(jìn)集成電路實踐教學(xué)的研究[J];數(shù)字技術(shù)與應(yīng)用;2012年07期
2 馬曉華;曹艷榮;郝躍;張月;;Hot carrier injection degradation under dynamic stress[J];Chinese Physics B;2011年03期
3 楊國勇,霍宗亮,王金延,毛凌鋒,王子歐,譚長華,許銘真;超薄柵MOS器件熱載流子應(yīng)力下SILC的產(chǎn)生機制(英文)[J];半導(dǎo)體學(xué)報;2003年06期
4 張進(jìn)城,郝躍,劉海波;通過直接?xùn)烹娏鳒y量研究PMOSFET's熱載流子損傷[J];半導(dǎo)體學(xué)報;2002年01期
5 張進(jìn)城,郝躍,朱志煒;MOS結(jié)構(gòu)中薄柵氧化層高場退火效應(yīng)的研究[J];物理學(xué)報;2001年08期
6 劉紅俠,郝躍,孫志;深亞微米MOS器件的熱載流子效應(yīng)[J];半導(dǎo)體學(xué)報;2001年06期
7 韓德棟,張國強,余學(xué)峰,任迪遠(yuǎn);注F短溝MOSFET的溝道熱載流子效應(yīng)[J];半導(dǎo)體學(xué)報;2001年05期
8 張衛(wèi)東,郝躍,湯玉生;深亞微米MOSFET熱載流子退化機理及建模的研究進(jìn)展[J];電子學(xué)報;1999年02期
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