中繼平臺上的SC-FDE系統(tǒng)方案研究與FPGA實(shí)現(xiàn)
發(fā)布時間：2019-02-23 21:17
【摘要】：隨著通信系統(tǒng)傳輸速率的提高,信道的多徑效應(yīng)對信號的影響越來越大。本文著重研究近年來逐漸興起的能夠抵抗多徑效應(yīng)的SC-FDE系統(tǒng)。本文首先研究無線多徑信道的特性,發(fā)現(xiàn)在無線信道中存在多徑效應(yīng),在其中傳輸信號會受到碼間干擾的影響。為了克服多徑效應(yīng),本文對均衡技術(shù)進(jìn)行了研究,著重對時域均衡和頻域均衡進(jìn)行了對比分析。通過研究發(fā)現(xiàn),時頻域的均衡器在系數(shù)確定方法和均衡器結(jié)構(gòu)設(shè)計方面大致相同。但是對于高速通信系統(tǒng),時域均衡器算法為指數(shù)級復(fù)雜度,不利于實(shí)現(xiàn)；頻域均衡器算法為線性對數(shù)級復(fù)雜度,在數(shù)字系統(tǒng)中容易實(shí)現(xiàn)。 由于SC-FDE系統(tǒng)對定時頻偏比較敏感,本文設(shè)計了適用于SC-FDE系統(tǒng)的同步方法。本文通過對經(jīng)典同步算法的研究發(fā)現(xiàn)Park算法比SC與Minn算法性能更好,同步準(zhǔn)確率更高,同時采用CAZAC序列作為Park算法的訓(xùn)練序列能夠改善系統(tǒng)的同步性能,消除原始Park算法的虛假峰值。為了對SC-FDE系統(tǒng)中的頻域處理資源進(jìn)行復(fù)用,本文研究了頻域同步方案,發(fā)現(xiàn)當(dāng)在某一個數(shù)據(jù)塊內(nèi)包含所有的同步信息時,就能夠使用頻域同步。針對這一發(fā)現(xiàn),本文提出了新型的頻域同步方案。該方案以頻域處理為基礎(chǔ),利用同步峰值在數(shù)據(jù)塊內(nèi)的位置信息,推導(dǎo)出同步碼字的起始位置。新方案與原始頻域同步方案相比同步頭設(shè)計簡單,同步性能更好,并且還可以復(fù)用SC-FDE系統(tǒng)資源,非常適合作為SC-FDE系統(tǒng)的同步方案。 最后,本文結(jié)合課題硬件平臺,將SC-FDE整體系統(tǒng)分為同步子系統(tǒng)與FDE子系統(tǒng),兩個子系統(tǒng)分別完成后,進(jìn)行聯(lián)合設(shè)計得到整體系統(tǒng)。整體系統(tǒng)采用改進(jìn)的頻域同步方式,使用線性頻域均衡,復(fù)用了FFT資源,在保證性能的前提下,節(jié)約了FPGA資源。
[Abstract]:With the increase of the transmission rate of communication system, the multipath effect of channel becomes more and more important. This paper focuses on the emerging SC-FDE system which can resist multipath effect in recent years. In this paper, we first study the characteristics of wireless multipath channel, and find that there is multipath effect in wireless channel, in which the transmission signal will be affected by inter-symbol interference (ISI). In order to overcome the multipath effect, the equalization technique is studied in this paper, and the time domain equalization and frequency domain equalization are compared and analyzed. It is found that the equalizer in time and frequency domain is similar in coefficient determination method and equalizer structure design. However, for high-speed communication systems, the time-domain equalizer algorithm is exponentially complex, which is not conducive to implementation; the frequency-domain equalizer algorithm is linear logarithmic complexity, which is easy to be implemented in digital systems. Because SC-FDE system is sensitive to timing frequency offset, a synchronization method suitable for SC-FDE system is designed in this paper. In this paper, we find that the performance of Park algorithm is better than that of SC and Minn algorithm, and the accuracy of synchronization is higher. At the same time, using CAZAC sequence as the training sequence of Park algorithm can improve the synchronization performance of the system. Eliminate the false peak of the original Park algorithm. In order to reuse the frequency domain processing resources in SC-FDE system, the frequency domain synchronization scheme is studied in this paper. It is found that frequency domain synchronization can be used when all synchronization information is included in a certain data block. In view of this discovery, a new frequency domain synchronization scheme is proposed in this paper. Based on frequency domain processing, the starting position of synchronous codewords is derived by using the position information of the synchronous peak value in the data block. Compared with the original frequency domain synchronization scheme, the new scheme has the advantages of simpler design of synchronization head, better synchronization performance and reuse of SC-FDE system resources. It is very suitable for synchronization scheme of SC-FDE system. Finally, the whole SC-FDE system is divided into synchronous subsystem and FDE subsystem. After the two subsystems are completed, the whole system is designed jointly. The whole system adopts the improved frequency domain synchronization mode and the linear frequency domain equalization. The FFT resources are reused, and the FPGA resources are saved on the premise of ensuring the performance.
【學(xué)位授予單位】：北京郵電大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN791;TN929.5
本文編號：2429212
[Abstract]:With the increase of the transmission rate of communication system, the multipath effect of channel becomes more and more important. This paper focuses on the emerging SC-FDE system which can resist multipath effect in recent years. In this paper, we first study the characteristics of wireless multipath channel, and find that there is multipath effect in wireless channel, in which the transmission signal will be affected by inter-symbol interference (ISI). In order to overcome the multipath effect, the equalization technique is studied in this paper, and the time domain equalization and frequency domain equalization are compared and analyzed. It is found that the equalizer in time and frequency domain is similar in coefficient determination method and equalizer structure design. However, for high-speed communication systems, the time-domain equalizer algorithm is exponentially complex, which is not conducive to implementation; the frequency-domain equalizer algorithm is linear logarithmic complexity, which is easy to be implemented in digital systems. Because SC-FDE system is sensitive to timing frequency offset, a synchronization method suitable for SC-FDE system is designed in this paper. In this paper, we find that the performance of Park algorithm is better than that of SC and Minn algorithm, and the accuracy of synchronization is higher. At the same time, using CAZAC sequence as the training sequence of Park algorithm can improve the synchronization performance of the system. Eliminate the false peak of the original Park algorithm. In order to reuse the frequency domain processing resources in SC-FDE system, the frequency domain synchronization scheme is studied in this paper. It is found that frequency domain synchronization can be used when all synchronization information is included in a certain data block. In view of this discovery, a new frequency domain synchronization scheme is proposed in this paper. Based on frequency domain processing, the starting position of synchronous codewords is derived by using the position information of the synchronous peak value in the data block. Compared with the original frequency domain synchronization scheme, the new scheme has the advantages of simpler design of synchronization head, better synchronization performance and reuse of SC-FDE system resources. It is very suitable for synchronization scheme of SC-FDE system. Finally, the whole SC-FDE system is divided into synchronous subsystem and FDE subsystem. After the two subsystems are completed, the whole system is designed jointly. The whole system adopts the improved frequency domain synchronization mode and the linear frequency domain equalization. The FFT resources are reused, and the FPGA resources are saved on the premise of ensuring the performance.
【學(xué)位授予單位】：北京郵電大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN791;TN929.5
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相關(guān)期刊論文 前4條
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