【摘要】：高性能的模數(shù)轉(zhuǎn)換器越來(lái)越多的應(yīng)用在國(guó)防、通信和高端家電等領(lǐng)域,是電子信息產(chǎn)業(yè)中的一項(xiàng)關(guān)鍵技術(shù)。隨著電子信息領(lǐng)域的發(fā)展,各種通信設(shè)備的工作速度不斷提高,因此對(duì)于高速模數(shù)轉(zhuǎn)換器的需求日趨迫切。傳統(tǒng)結(jié)構(gòu)的ADC在保證精度的情況下,速度實(shí)現(xiàn)幾乎達(dá)到了極限。因此,將單通道的ADC并行化是突破轉(zhuǎn)換速率的限制并不犧牲精度的有效方法。多通道時(shí)間交織技術(shù)存在著固有的弊端,即通道間的增益失配、失調(diào)失配和采樣時(shí)刻失配會(huì)降低系統(tǒng)精度,需要校正技術(shù)消除誤差。本文首先基于CMOS Smic0.18μm工藝設(shè)計(jì)了一款12位50MHz的單通道流水線ADC,在輸入561.523k Hz的正弦信號(hào)時(shí),信噪失真比(SNDR)達(dá)到70.3581d B,動(dòng)態(tài)無(wú)雜散范圍(SFDR)為77.9108d B,有效位數(shù)(ENOB)為11.5137位。在此基礎(chǔ)上,詳細(xì)分析了雙通道時(shí)間交織流水線ADC的失配產(chǎn)生原因,通過(guò)數(shù)學(xué)推導(dǎo)將失調(diào)失配、增益失配和采樣時(shí)刻失配對(duì)系統(tǒng)精度的影響進(jìn)行量化,并利用Matlab建模仿真驗(yàn)證三種失配在時(shí)間交織系統(tǒng)中產(chǎn)生的影響。針對(duì)誤差消除,采用基于LMS-FIR及CIC內(nèi)插濾波的校正算法,設(shè)計(jì)了12位100M的雙通道時(shí)間交織流水線ADC系統(tǒng)。仿真結(jié)果表明,采樣時(shí)鐘100MHz,輸入信號(hào)頻率561.523k Hz時(shí),經(jīng)過(guò)校正后系統(tǒng)輸出的動(dòng)態(tài)無(wú)雜散范圍達(dá)到75.98d B。
[Abstract]:High performance analog-to-digital converters are increasingly used in defense, communications and high-end home appliances, which is a key technology in the electronic information industry. With the development of electronic information field, the working speed of various communication equipments is increasing, so the demand of high speed A / D converter is becoming more and more urgent. Under the condition of guaranteeing precision, the speed of ADC with traditional structure has almost reached the limit. Therefore, parallelization of single channel ADC is an effective method to break through the limit of conversion rate without sacrificing precision. Multi-channel time interleaving technology has its inherent disadvantages, that is, gain mismatch between channels, mismatch between channels and mismatch at sampling time will reduce the system precision, and the correction technique is needed to eliminate the error. In this paper, we first design a 12-bit 50MHz single-channel pipeline ADC, based on CMOS Smic0.18 渭 m process. When we input the sine signal of 561.523k Hz, the signal-to-noise distortion ratio (SNDR) reaches 70.3581dB, and the dynamic non-spurious range (SFDR) is 77.9108dB. The effective digit (ENOB) is 11.5137 bits. On this basis, the causes of mismatch of two-channel time-interleaved pipeline ADC are analyzed in detail. The effects of mismatch, gain mismatch and sampling time mismatch on the system precision are quantified by mathematical derivation. The effects of three mismatches on time interleaving systems are verified by Matlab modeling and simulation. Based on LMS-FIR and CIC interpolation filtering, a 12-bit 100m dual channel time interleaved pipeline ADC system is designed for error cancellation. The simulation results show that when the sampling clock is 100MHz and the input signal frequency is 561.523k Hz, the dynamic spurious range of the output is 75.98dB after correction.
【學(xué)位授予單位】：哈爾濱工業(yè)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN792

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本文編號(hào)：2425301