高速PCB設(shè)計(jì)中信號及電源完整性分析與應(yīng)用
發(fā)布時(shí)間：2019-01-05 03:58
【摘要】：隨著集成電路技術(shù)的快速發(fā)展,高速電路中信號及電源完整性問題日益明顯,對電路系統(tǒng)的穩(wěn)定性造成了極大影響,并已成為電子工程師在電路設(shè)計(jì)過程中不可避免的問題之一,正確處理設(shè)計(jì)及調(diào)試過程中的信號及電源完整性問題已成為高速電路設(shè)計(jì)中的重要環(huán)節(jié)。本文分析了無源元件及傳輸線的高頻特性,以及高速互連設(shè)計(jì)中存在的反射、串?dāng)_、時(shí)序及電源完整性問題的產(chǎn)生原因,并確定了各類噪聲及時(shí)序問題的優(yōu)化方法。在高速互連理論的基礎(chǔ)上對一款以i.MX6Q為核心的復(fù)雜高速電路板進(jìn)行設(shè)計(jì),利用IBIS模型和HyperLynx仿真工具在板級設(shè)計(jì)中對信號及電源完整性問題進(jìn)行仿真分析及優(yōu)化。根據(jù)仿真結(jié)果制定布線約束及去耦規(guī)則,建立了完整的設(shè)計(jì)及仿真過程,使串?dāng)_噪聲、反射噪聲、時(shí)序誤差及電源噪聲控制在可接受的范圍內(nèi)。系統(tǒng)使用八層PCB設(shè)計(jì),優(yōu)化布局布線使高速互連串?dāng)_噪聲峰值降低為20mV;使用ODT功能控制反射噪聲在極小的幅度內(nèi);控制線長使命令線、控制線及數(shù)據(jù)線滿足時(shí)序要求;優(yōu)化PDN阻抗曲線,減小電源噪聲,最終完成PCB的設(shè)計(jì)及調(diào)試。本文在高速PCB設(shè)計(jì)及仿真的研究中所得的仿真數(shù)據(jù)、優(yōu)化方法及結(jié)論可以為與此相關(guān)的高速電路設(shè)計(jì)提供一定參考。
[Abstract]:With the rapid development of integrated circuit technology, the problem of signal and power integrity in high-speed circuits becomes more and more obvious, which has a great impact on the stability of circuit system. It has become one of the inevitable problems in the circuit design of electronic engineers. It has become an important link in the design of high-speed circuits to correctly deal with the problems of signal and power supply integrity in the process of design and debugging. This paper analyzes the high frequency characteristics of passive components and transmission lines, and the causes of the problems of reflection, crosstalk, timing and power supply integrity in the design of high speed interconnection, and determines the optimization methods for all kinds of noise and timing problems. Based on the theory of high speed interconnection, a complex high speed circuit board with i.MX6Q as its core is designed. The signal and power integrity problems are simulated and optimized by using IBIS model and HyperLynx simulation tool in board level design. According to the simulation results, the routing constraints and decoupling rules are formulated, and a complete design and simulation process is established to control crosstalk noise, reflection noise, timing error and power supply noise within an acceptable range. The system uses 8-layer PCB design, optimizes layout and wiring to reduce the peak value of crosstalk noise to 20mV, uses ODT function to control the reflected noise in a minimum amplitude, and the control line length makes the command line, control line and data line meet the requirements of time sequence. The impedance curve of PDN is optimized to reduce the noise of power supply. Finally, the design and debugging of PCB are finished. The simulation data, optimization methods and conclusions obtained in the research of high speed PCB design and simulation can provide some reference for the design of high speed circuits.
【學(xué)位授予單位】：中國礦業(yè)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2016
【分類號】：TN41
本文編號：2401230
[Abstract]:With the rapid development of integrated circuit technology, the problem of signal and power integrity in high-speed circuits becomes more and more obvious, which has a great impact on the stability of circuit system. It has become one of the inevitable problems in the circuit design of electronic engineers. It has become an important link in the design of high-speed circuits to correctly deal with the problems of signal and power supply integrity in the process of design and debugging. This paper analyzes the high frequency characteristics of passive components and transmission lines, and the causes of the problems of reflection, crosstalk, timing and power supply integrity in the design of high speed interconnection, and determines the optimization methods for all kinds of noise and timing problems. Based on the theory of high speed interconnection, a complex high speed circuit board with i.MX6Q as its core is designed. The signal and power integrity problems are simulated and optimized by using IBIS model and HyperLynx simulation tool in board level design. According to the simulation results, the routing constraints and decoupling rules are formulated, and a complete design and simulation process is established to control crosstalk noise, reflection noise, timing error and power supply noise within an acceptable range. The system uses 8-layer PCB design, optimizes layout and wiring to reduce the peak value of crosstalk noise to 20mV, uses ODT function to control the reflected noise in a minimum amplitude, and the control line length makes the command line, control line and data line meet the requirements of time sequence. The impedance curve of PDN is optimized to reduce the noise of power supply. Finally, the design and debugging of PCB are finished. The simulation data, optimization methods and conclusions obtained in the research of high speed PCB design and simulation can provide some reference for the design of high speed circuits.
【學(xué)位授予單位】：中國礦業(yè)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2016
【分類號】：TN41
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