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【摘要】：可逆邏輯電路是僅包含可逆運算的新型電路，可以根除源于信息損失的能耗和發(fā)熱，是研究和實現(xiàn)超低功耗集成電路、量子計算機以及信息安全等的基礎(chǔ)和關(guān)鍵。可逆邏輯綜合就是利用給定的可逆邏輯門，按照可逆網(wǎng)絡(luò)無扇入扇出、無反饋等約束條件和限制，實現(xiàn)具備預(yù)期邏輯功能且盡可能優(yōu)化的可逆邏輯電路。因此，對可逆邏輯綜合方法的研究具有重要的理論意義和應(yīng)用前景。 本文一方面針對可逆邏輯綜合的需要，以顯著提高可逆邏輯綜合算法的勝任規(guī)模和優(yōu)化程度為目標(biāo)，對常規(guī)（非可逆）邏輯綜合、優(yōu)化方面著名的Espresso算法進(jìn)行了移植和實現(xiàn)。通過分析常規(guī)的“積之和”表達(dá)式和便于可逆邏輯門實現(xiàn)的“積之異或和”表達(dá)式之間的差異與聯(lián)系，推導(dǎo)出了它們之間相互轉(zhuǎn)換的方法，然后據(jù)此方法討論了將Espresso算法修改和移植用于可逆邏輯綜合的思路和要點。通過理論推導(dǎo)和實例分析驗證了上述移植方法應(yīng)用于可逆邏輯綜合的有效性，并對改進(jìn)的算法進(jìn)行了編程實現(xiàn)和實驗檢驗。另一方面，針對可逆邏輯電路的特點，討論了利用常用的可逆邏輯門和擴(kuò)展的可逆邏輯門構(gòu)造可逆邏輯電路的方法和步驟；重點研究了通過識別可逆邏輯表達(dá)式提取電路結(jié)構(gòu)信息，并加以圖形化顯示的有效方法和可行算法，并對上述方法和算法進(jìn)行了編程實現(xiàn)、實驗驗證和有效改進(jìn)。 希望本文對于可逆邏輯綜合、優(yōu)化方面的研究，，特別是現(xiàn)行（非可逆）邏輯綜合、優(yōu)化算法面向可逆邏輯的移植、改進(jìn)，以及可逆邏輯設(shè)計結(jié)果的圖形化表達(dá)和交互式分析、驗證，能夠具有較大參考價值甚至起到一定推動作用。
[Abstract]:Reversible logic circuit is a new type of circuit which contains only reversible operation. It can eliminate the energy consumption and heat caused by information loss. It is the foundation and key to research and implement ultralow power integrated circuit, quantum computer and information security. Reversible logic synthesis is to realize the reversible logic circuit with expected logic function and optimize as far as possible, according to the constraints and limitations of reversible network, such as no fan in and out, no feedback and so on, using a given reversible logic gate. Therefore, the research of reversible logic synthesis method has important theoretical significance and application prospect. In this paper, aiming at the need of reversible logic synthesis, aiming at improving the scale and optimization degree of reversible logic synthesis algorithm, the famous Espresso algorithm is transplanted and implemented in the aspect of conventional (non-reversible) logic synthesis and optimization. By analyzing the difference and relation between the expression of "sum of product" and the expression of "sum of products" which is easy to realize by reversible logic gate, the method of conversion between them is deduced. Based on this method, the idea and key points of modifying and transplanting Espresso algorithm for reversible logic synthesis are discussed. The validity of the proposed method in reversible logic synthesis is verified by theoretical derivation and example analysis. The improved algorithm is programmed and tested experimentally. On the other hand, according to the characteristics of reversible logic circuits, the methods and steps of constructing reversible logic circuits using common reversible logic gates and extended reversible logic gates are discussed. The effective methods and feasible algorithms for extracting circuit structure information by identifying reversible logic expressions and displaying them graphically are studied emphatically. The above methods and algorithms are implemented by programming, and verified by experiments and improved effectively. It is hoped that the research on reversible logic synthesis, optimization, especially the current (non-reversible) logic synthesis, the optimization algorithm oriented to the transplantation and improvement of reversible logic, and the graphical representation and interactive analysis of reversible logic design results will be carried out in this paper. Verification, can have greater reference value and even play a role in promoting.
【學(xué)位授予單位】：東華大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN791

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