基于FPGA的多通道高速數(shù)據(jù)采集系統(tǒng)設(shè)計
發(fā)布時間：2018-12-08 16:46
【摘要】：隨著計算機和微電子技術(shù)的發(fā)展,雷達、通信等眾多應(yīng)用領(lǐng)域?qū)τ跀?shù)據(jù)采集系統(tǒng)提出了更高的要求,數(shù)據(jù)采集正在向著多通道、高采樣率、高分辨率、大容量存儲和高速傳輸速率方向快速發(fā)展。本文根據(jù)當前國內(nèi)外的研究現(xiàn)狀,針對某雷達成像項目中數(shù)據(jù)采集系統(tǒng)的指標要求,設(shè)計了一款基于FPGA的多通道高速數(shù)據(jù)采集系統(tǒng),該系統(tǒng)以FPGA作為整個系統(tǒng)的控制、處理核心,通過AD模塊實現(xiàn)數(shù)據(jù)的采集與模數(shù)轉(zhuǎn)換,并將采集到的數(shù)據(jù)傳輸至FPGA,在FPGA內(nèi)進行處理后將數(shù)據(jù)傳輸至相關(guān)板卡,同時通過PCI接口技術(shù)實現(xiàn)FPGA與上位機端的通信。FPGA作為系統(tǒng)的控制核心芯片可提高系統(tǒng)穩(wěn)定性、減少設(shè)備體積。本文分為硬件設(shè)計和軟件設(shè)計兩部分,提出了高速數(shù)據(jù)采集系統(tǒng)的設(shè)計方案。硬件設(shè)計包括各器件的選型、原理分析、外圍電路設(shè)計及PCB設(shè)計,軟件設(shè)計作為本文的核心部分,包括FPGA的邏輯設(shè)計與仿真測試,實現(xiàn)了AD模塊的數(shù)據(jù)采集功能、基于PCI接口的C模式工作狀態(tài)下FPGA與上位機端的通信功能以及基于GTX模塊的高速串行數(shù)據(jù)傳輸功能。論文的最后通過搭建硬件測試平臺,完成系統(tǒng)軟硬件聯(lián)調(diào)工作,給出了相關(guān)測試結(jié)果,進一步驗證了方案的可行性。論文的框架圍繞AD模塊、PCI模塊及GTX模塊展開,該系統(tǒng)具有多通道、高采樣率、高數(shù)據(jù)傳輸帶寬等特點。論文的研究工作為后續(xù)的圖像處理提供了有力的支持,在高速數(shù)據(jù)采集及其相關(guān)領(lǐng)域有著廣泛的應(yīng)用前景。
[Abstract]:With the development of computer and microelectronics technology, radar, communication and many other application fields put forward higher requirements for data acquisition system. Data acquisition is towards multi-channel, high sampling rate, high resolution. Large-capacity storage and high-speed transmission rate are developing rapidly. According to the current research situation at home and abroad, a multi-channel high-speed data acquisition system based on FPGA is designed according to the requirement of data acquisition system in a radar imaging project. The system takes FPGA as the control of the whole system. The core of processing is to realize data acquisition and analog-to-digital conversion through AD module, and transfer the collected data to FPGA, after processing in FPGA, and then transfer the data to the relevant card. At the same time, the communication between FPGA and upper computer can be realized by PCI interface technology. As the control core of the system, FPGA can improve the stability of the system and reduce the volume of the equipment. This paper is divided into two parts: hardware design and software design. The hardware design includes the selection of each device, principle analysis, peripheral circuit design and PCB design, software design as the core part of this paper, including the logic design and simulation test of FPGA. The data acquisition function of AD module is realized. The communication function between FPGA and the upper computer in C mode based on PCI interface and the high speed serial data transmission function based on GTX module. At the end of the paper, the hardware and software of the system are adjusted by building the hardware test platform, and the related test results are given, and the feasibility of the scheme is further verified. The framework of this paper is based on AD module, PCI module and GTX module. The system has the characteristics of multi-channel, high sampling rate and high data transmission bandwidth. The research work in this paper provides a powerful support for the subsequent image processing and has a wide application prospect in high-speed data acquisition and related fields.
【學位授予單位】：北京理工大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN791;TP274.2
本文編號：2368665
[Abstract]:With the development of computer and microelectronics technology, radar, communication and many other application fields put forward higher requirements for data acquisition system. Data acquisition is towards multi-channel, high sampling rate, high resolution. Large-capacity storage and high-speed transmission rate are developing rapidly. According to the current research situation at home and abroad, a multi-channel high-speed data acquisition system based on FPGA is designed according to the requirement of data acquisition system in a radar imaging project. The system takes FPGA as the control of the whole system. The core of processing is to realize data acquisition and analog-to-digital conversion through AD module, and transfer the collected data to FPGA, after processing in FPGA, and then transfer the data to the relevant card. At the same time, the communication between FPGA and upper computer can be realized by PCI interface technology. As the control core of the system, FPGA can improve the stability of the system and reduce the volume of the equipment. This paper is divided into two parts: hardware design and software design. The hardware design includes the selection of each device, principle analysis, peripheral circuit design and PCB design, software design as the core part of this paper, including the logic design and simulation test of FPGA. The data acquisition function of AD module is realized. The communication function between FPGA and the upper computer in C mode based on PCI interface and the high speed serial data transmission function based on GTX module. At the end of the paper, the hardware and software of the system are adjusted by building the hardware test platform, and the related test results are given, and the feasibility of the scheme is further verified. The framework of this paper is based on AD module, PCI module and GTX module. The system has the characteristics of multi-channel, high sampling rate and high data transmission bandwidth. The research work in this paper provides a powerful support for the subsequent image processing and has a wide application prospect in high-speed data acquisition and related fields.
【學位授予單位】：北京理工大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN791;TP274.2
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，本文編號：2368665
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