基于改進(jìn)量子進(jìn)化算法的3D NoC測(cè)試TSV優(yōu)化
發(fā)布時(shí)間：2018-12-07 12:39
【摘要】：針對(duì)硅通孔(through-silicon-via,TSV)的生產(chǎn)成本高,占用面積大等問(wèn)題,首先對(duì)三維片上網(wǎng)絡(luò)(3D NoC)進(jìn)行測(cè)試規(guī)劃研究,將測(cè)試規(guī)劃得到的最短測(cè)試時(shí)間作為約束條件,采用改進(jìn)的量子進(jìn)化算法優(yōu)化測(cè)試占用的TSV數(shù)量,將各層的TSV按照需求進(jìn)行配置,并將TSV合理有效地分配給各個(gè)內(nèi)核,以在有限的TSV數(shù)量下,降低硬件開(kāi)銷(xiāo),提高利用率,同時(shí),探討TSV的分配對(duì)測(cè)試時(shí)間的影響。算法中,引入量子旋轉(zhuǎn)門(mén)旋轉(zhuǎn)角動(dòng)態(tài)調(diào)整策略和量子變異策略,以提高算法的全局尋優(yōu)能力和收斂速度,避免陷入局部最優(yōu)解。將ITC’02基準(zhǔn)電路作為仿真實(shí)驗(yàn)對(duì)象,由實(shí)驗(yàn)結(jié)果可得,本算法能夠快速地收斂到最佳解,有效的減小了測(cè)試時(shí)間,優(yōu)化了TSV數(shù)量,提高了TSV的利用率。
[Abstract]:Aiming at the problems of high production cost and large area occupied by silicon through hole (through-silicon-via,TSV), the test planning of 3D NoC is carried out firstly, and the shortest test time obtained from the test planning is taken as the constraint condition. The improved quantum evolutionary algorithm is used to optimize the amount of TSV consumed by the test, and the TSV of each layer is configured according to the requirements, and the TSV is allocated to each kernel reasonably and effectively, so as to reduce the hardware overhead and improve the utilization ratio under the limited TSV number. At the same time, the effect of TSV on the test time was discussed. In order to improve the global optimization ability and convergence speed of the algorithm, quantum rotation gate rotation angle dynamic adjustment strategy and quantum mutation strategy are introduced to avoid falling into the local optimal solution. The ITC'02 reference circuit is taken as the object of simulation experiment. From the experimental results, the algorithm can quickly converge to the optimal solution, effectively reduce the test time, optimize the number of TSV, and improve the utilization rate of TSV.
【作者單位】： 桂林電子科技大學(xué)電子工程與自動(dòng)化學(xué)院;廣西自動(dòng)檢測(cè)技術(shù)與儀器重點(diǎn)實(shí)驗(yàn)室;
【基金】：國(guó)家自然科學(xué)基金(61561012) 廣西自然科學(xué)基金(2014GXNSFAA118398)資助項(xiàng)目
【分類(lèi)號(hào)】：TN407;TP18
本文編號(hào)：2367220
[Abstract]:Aiming at the problems of high production cost and large area occupied by silicon through hole (through-silicon-via,TSV), the test planning of 3D NoC is carried out firstly, and the shortest test time obtained from the test planning is taken as the constraint condition. The improved quantum evolutionary algorithm is used to optimize the amount of TSV consumed by the test, and the TSV of each layer is configured according to the requirements, and the TSV is allocated to each kernel reasonably and effectively, so as to reduce the hardware overhead and improve the utilization ratio under the limited TSV number. At the same time, the effect of TSV on the test time was discussed. In order to improve the global optimization ability and convergence speed of the algorithm, quantum rotation gate rotation angle dynamic adjustment strategy and quantum mutation strategy are introduced to avoid falling into the local optimal solution. The ITC'02 reference circuit is taken as the object of simulation experiment. From the experimental results, the algorithm can quickly converge to the optimal solution, effectively reduce the test time, optimize the number of TSV, and improve the utilization rate of TSV.
【作者單位】： 桂林電子科技大學(xué)電子工程與自動(dòng)化學(xué)院;廣西自動(dòng)檢測(cè)技術(shù)與儀器重點(diǎn)實(shí)驗(yàn)室;
【基金】：國(guó)家自然科學(xué)基金(61561012) 廣西自然科學(xué)基金(2014GXNSFAA118398)資助項(xiàng)目
【分類(lèi)號(hào)】：TN407;TP18
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