多通道高速時(shí)鐘數(shù)據(jù)恢復(fù)電路設(shè)計(jì)
發(fā)布時(shí)間：2018-11-26 10:07
【摘要】：隨著通信技術(shù)的高速發(fā)展,超級(jí)計(jì)算機(jī)、智能終端和多媒體網(wǎng)絡(luò)等海量數(shù)據(jù)的快速傳輸,用戶對(duì)數(shù)據(jù)的傳輸提出了更高的要求。由于串行通信高速率的優(yōu)點(diǎn),使其逐漸成為接口的主流技術(shù)。IEEE 802.3ae協(xié)議定義了一種高速的、靈活的信號(hào)傳輸模式。采用多通道的XAUI(10 Ggigbit Attachment Unit Interface)接口,對(duì)信號(hào)進(jìn)行8/10 bit編碼,完成10 Gbps數(shù)據(jù)通信。CDR(Clock and Data Recovery)是串行通信技術(shù)領(lǐng)域最關(guān)鍵的電路,也是高速接口速率提升的瓶頸,工作在協(xié)議的物理層部分,完成時(shí)鐘的生成和數(shù)據(jù)的重定時(shí),對(duì)整個(gè)通信系統(tǒng)的性能起到了決定性作用。本文基于標(biāo)準(zhǔn)SMIC 0.13μm CMOS工藝,采用自頂向下的設(shè)計(jì)方法,不斷對(duì)CDR環(huán)路和單元電路進(jìn)行優(yōu)化,完成四通道、總有效數(shù)據(jù)率為10 Gbps的高速C DR電路設(shè)計(jì)。本課題的主要內(nèi)容是:1)對(duì)PI(Phase Interpolator)電路進(jìn)行詳細(xì)的理論分析。把PI的權(quán)重因子分為線性的和非線性的分別討論,找到一種非線性的權(quán)重因子可以使PI輸出信號(hào)的相位有很好的線性度。同時(shí),討論了PI輸入信號(hào)的上升時(shí)間、輸入信號(hào)的相位差和輸出節(jié)點(diǎn)的時(shí)間常數(shù)三者相互作用對(duì)PI線性度的影響。2)本次CDR電路根據(jù)XAUI接口標(biāo)準(zhǔn)選擇四個(gè)通道,每個(gè)通道共享PLL電路提供的參考時(shí)鐘。采用模擬正交相位插值結(jié)構(gòu)的CDR電路,既提高了PI最小相位跳躍精度,又適用于高速電路。電路設(shè)計(jì)時(shí),先對(duì)環(huán)路進(jìn)行適當(dāng)?shù)母倪M(jìn),加入了差分轉(zhuǎn)單端電路,減小了恢復(fù)時(shí)鐘的峰峰值抖動(dòng)。然后,根據(jù)單元電路設(shè)計(jì)需求,鑒相器選擇半速率的Alexander鑒相器,電荷泵選擇全差分結(jié)構(gòu),并把PI電路的電阻負(fù)載改進(jìn)為對(duì)稱負(fù)載。CDR電路版圖的面積為532μm*426μm。單通道輸入偽隨機(jī)序列碼的長(zhǎng)度為223-1,數(shù)據(jù)的波特率為3.125 Gbps。仿真結(jié)果表明:在SS工藝角下鎖定時(shí)間為6.2μs,恢復(fù)的時(shí)鐘信號(hào)峰峰值抖動(dòng)為28.8μs,功耗最大在FF的工藝角下為17.2 mW,滿足設(shè)計(jì)要求。
[Abstract]:With the rapid development of communication technology and the rapid transmission of massive data such as supercomputers, intelligent terminals and multimedia networks, users have put forward higher requirements for data transmission. Because of the high speed of serial communication, it has gradually become the mainstream technology of interface. IEEE 802.3ae protocol defines a high speed and flexible signal transmission mode. Using the multi-channel XAUI (10 Ggigbit Attachment Unit Interface) interface) to encode the signal with 8 / 10 bit and complete the 10 Gbps data communication. CDR (Clock and Data Recovery) is the most important circuit in the field of serial communication technology, and it is also the bottleneck of increasing the speed of high-speed interface. Working in the physical layer of the protocol, clock generation and data retiming play a decisive role in the performance of the whole communication system. Based on the standard SMIC 0.13 渭 m CMOS process, the top-down design method is used to optimize the circuit of CDR loop and unit continuously, and to complete the design of high-speed C DR circuit with four channels and a total effective data rate of 10 Gbps. The main contents of this paper are as follows: 1) theoretical analysis of PI (Phase Interpolator) circuit is carried out in detail. The weight factor of PI is divided into linear and nonlinear, and a nonlinear weight factor is found to make the phase of PI output signal have good linearity. At the same time, the influence of the rise time of the PI input signal, the phase difference of the input signal and the time constant of the output node on the linearity of the PI is discussed. 2) the CDR circuit selects four channels according to the XAUI interface standard. Each channel shares the reference clock provided by the PLL circuit. The CDR circuit with analog orthogonal phase interpolation not only improves the minimum phase jump accuracy of PI, but also is suitable for high speed circuits. When the circuit is designed, the loop is improved properly and the differential switching circuit is added to reduce the peak and peak jitter of the recovery clock. Then, according to the design requirements of the cell circuit, the phase discriminator selects the Alexander phase detector with half rate and the charge pump selects the fully differential structure. The resistive load of the PI circuit is improved to a symmetrical load. The area of the CDR circuit layout is 532 渭 m ~ 426 渭 m. The length of single-channel input pseudorandom sequence code is 223-1, and the baud rate of data is 3.125 Gbps.. The simulation results show that the locking time is 6.2 渭 s at the SS process angle, the peak jitter of the recovered clock signal is 28.8 渭 s, and the maximum power consumption is 17.2 mW, at the FF process angle.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN402
，
本文編號(hào)：2358247
[Abstract]:With the rapid development of communication technology and the rapid transmission of massive data such as supercomputers, intelligent terminals and multimedia networks, users have put forward higher requirements for data transmission. Because of the high speed of serial communication, it has gradually become the mainstream technology of interface. IEEE 802.3ae protocol defines a high speed and flexible signal transmission mode. Using the multi-channel XAUI (10 Ggigbit Attachment Unit Interface) interface) to encode the signal with 8 / 10 bit and complete the 10 Gbps data communication. CDR (Clock and Data Recovery) is the most important circuit in the field of serial communication technology, and it is also the bottleneck of increasing the speed of high-speed interface. Working in the physical layer of the protocol, clock generation and data retiming play a decisive role in the performance of the whole communication system. Based on the standard SMIC 0.13 渭 m CMOS process, the top-down design method is used to optimize the circuit of CDR loop and unit continuously, and to complete the design of high-speed C DR circuit with four channels and a total effective data rate of 10 Gbps. The main contents of this paper are as follows: 1) theoretical analysis of PI (Phase Interpolator) circuit is carried out in detail. The weight factor of PI is divided into linear and nonlinear, and a nonlinear weight factor is found to make the phase of PI output signal have good linearity. At the same time, the influence of the rise time of the PI input signal, the phase difference of the input signal and the time constant of the output node on the linearity of the PI is discussed. 2) the CDR circuit selects four channels according to the XAUI interface standard. Each channel shares the reference clock provided by the PLL circuit. The CDR circuit with analog orthogonal phase interpolation not only improves the minimum phase jump accuracy of PI, but also is suitable for high speed circuits. When the circuit is designed, the loop is improved properly and the differential switching circuit is added to reduce the peak and peak jitter of the recovery clock. Then, according to the design requirements of the cell circuit, the phase discriminator selects the Alexander phase detector with half rate and the charge pump selects the fully differential structure. The resistive load of the PI circuit is improved to a symmetrical load. The area of the CDR circuit layout is 532 渭 m ~ 426 渭 m. The length of single-channel input pseudorandom sequence code is 223-1, and the baud rate of data is 3.125 Gbps.. The simulation results show that the locking time is 6.2 渭 s at the SS process angle, the peak jitter of the recovered clock signal is 28.8 渭 s, and the maximum power consumption is 17.2 mW, at the FF process angle.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN402
，
本文編號(hào)：2358247
本文鏈接：http://sikaile.net/kejilunwen/dianzigongchenglunwen/2358247.html
最近更新
教材專著
