基于SystemC的1553B總線事務(wù)級(jí)模型設(shè)計(jì)
發(fā)布時(shí)間：2018-11-21 12:04
【摘要】：隨著集成電路規(guī)模的不斷增大,電路性能提升的同時(shí)也給設(shè)計(jì)和驗(yàn)證工作帶來了新的挑戰(zhàn)。在傳統(tǒng)的超大規(guī)模集成電路的設(shè)計(jì)流程中,硬件的設(shè)計(jì)與軟件的設(shè)計(jì)工作是分開進(jìn)行的,并且軟件的設(shè)計(jì)往往要滯后于硬件,在整合軟硬件時(shí)如果想要對(duì)設(shè)計(jì)進(jìn)行修改又不得不重新劃分軟硬件的職能,并從頭開始設(shè)計(jì)。這就帶來了時(shí)間和精力上的浪費(fèi)。對(duì)于驗(yàn)證而言,使用傳統(tǒng)高級(jí)語言的驗(yàn)證程序與周期精確的硬件描述語言進(jìn)行混合仿真,速度很慢,往往會(huì)導(dǎo)致整個(gè)進(jìn)度的滯后。這在追求產(chǎn)品快速更新?lián)屨际袌?chǎng)的今天是難以忍受的。為了解決以上的問題,可以在設(shè)計(jì)流程中使用System C語言先進(jìn)行系統(tǒng)級(jí)的設(shè)計(jì),軟硬件的設(shè)計(jì)工作可以同步進(jìn)行。各個(gè)單元采用事務(wù)級(jí)的建模方法,設(shè)計(jì)周期更短并且仿真速度比傳統(tǒng)的RTL模型快2~3個(gè)數(shù)量級(jí),通過驗(yàn)證后再將軟硬件翻譯成對(duì)應(yīng)的高級(jí)語言和硬件描述語言,從而達(dá)到節(jié)約時(shí)間的目的。本文設(shè)計(jì)的1553B總線事務(wù)級(jí)模型是實(shí)驗(yàn)室事務(wù)級(jí)So C驗(yàn)證平臺(tái)的一部分,可以對(duì)基于1553B總線的IP核完成快速的驗(yàn)證工作。采用System C語言進(jìn)行事務(wù)級(jí)的建模,建模標(biāo)準(zhǔn)采用的是TLM2.0,模塊之間的通訊更加規(guī)范。首先介紹1553B總線的應(yīng)用背景、發(fā)展現(xiàn)狀以及對(duì)其進(jìn)行建模的必要性,利用System C進(jìn)行事務(wù)級(jí)建模的機(jī)制,接著提出了1553B總線模型的整體設(shè)計(jì)方案,完成總線控制器接口(BC接口)、遠(yuǎn)程終端接口(RT接口)和事務(wù)級(jí)總線通道的設(shè)計(jì)工作。在總線模型的各個(gè)部分設(shè)計(jì)工作完成后,為其搭建測(cè)試平臺(tái)并提出兩種測(cè)試方案,一是對(duì)其功能點(diǎn)進(jìn)行點(diǎn)對(duì)點(diǎn)的測(cè)試,驗(yàn)證功能的正確性,二是采用對(duì)1553B總線16bit指令字進(jìn)行窮舉的方式對(duì)總線模型進(jìn)行全覆蓋測(cè)試,評(píng)估模型的仿真速度。通過初步的測(cè)試后將該事務(wù)級(jí)總線模型掛載到LEON3 So C驗(yàn)證平臺(tái)上進(jìn)行最終的測(cè)試,并在1553B總線模型的RT端掛載一個(gè)真實(shí)的IP——DES密碼算法模塊,完成總線模型的驗(yàn)證工作。經(jīng)驗(yàn)證該1553B總線事務(wù)級(jí)模型功能實(shí)現(xiàn)正確,成功完成了與So C驗(yàn)證平臺(tái)的通信,并且相比于傳統(tǒng)的RTL模型提高了仿真速度,可以用于1553B總線IP核的快速驗(yàn)證工作。
[Abstract]:With the increasing scale of integrated circuits, the improvement of circuit performance brings new challenges to the design and verification work. In the traditional design flow of VLSI, the design of hardware and software are carried out separately, and the design of software often lags behind that of hardware. When integrating software and hardware, if you want to modify the design, you have to redivide the functions of the software and hardware, and design from scratch. This creates a waste of time and energy. For verification, using traditional high-level language verifier and cycle precise hardware description language for hybrid simulation, the speed is very slow, often lead to the whole progress of the lag. This in the pursuit of rapid product updates to seize the market today is intolerable. In order to solve the above problems, the system level design can be carried out by using System C language in the design process, and the design of software and hardware can be carried out synchronously. Each unit adopts transactional modeling method, the design cycle is shorter and the simulation speed is 2 ~ 3 orders of magnitude faster than the traditional RTL model. After verification, the software and hardware are translated into the corresponding high-level language and hardware description language. In order to achieve the goal of saving time. The transaction level model of 1553B bus designed in this paper is a part of the laboratory transactional So C verification platform, which can complete the fast verification of the IP core based on 1553B bus. System C language is used for transactional modeling. The modeling standard is the communication between TLM2.0, modules. This paper first introduces the application background of 1553B bus, the present situation of its development and the necessity of modeling it, the mechanism of transaction level modeling using System C, and then puts forward the overall design scheme of 1553B bus model. The design of bus controller interface (BC interface), remote terminal interface (RT interface) and transactional bus channel is completed. After the design of each part of the bus model is finished, the test platform is built and two test schemes are put forward. One is to test the function point to verify the correctness of the function. The second is to test the bus model by exhaustive 16bit instruction word of 1553B bus and evaluate the simulation speed of the model. After a preliminary test, the transactional bus model is mounted on the LEON3 So C verification platform for final test, and a real IP--DES cryptographic algorithm module is mounted on the RT side of the 1553B bus model to complete the verification of the bus model. It is proved that the 1553B bus transaction level model is correct, and the communication with the So C verification platform is successfully completed. Compared with the traditional RTL model, the simulation speed is improved, and it can be used for the fast verification of the 1553B bus IP core.
【學(xué)位授予單位】：哈爾濱工業(yè)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN47
本文編號(hào)：2346913
[Abstract]:With the increasing scale of integrated circuits, the improvement of circuit performance brings new challenges to the design and verification work. In the traditional design flow of VLSI, the design of hardware and software are carried out separately, and the design of software often lags behind that of hardware. When integrating software and hardware, if you want to modify the design, you have to redivide the functions of the software and hardware, and design from scratch. This creates a waste of time and energy. For verification, using traditional high-level language verifier and cycle precise hardware description language for hybrid simulation, the speed is very slow, often lead to the whole progress of the lag. This in the pursuit of rapid product updates to seize the market today is intolerable. In order to solve the above problems, the system level design can be carried out by using System C language in the design process, and the design of software and hardware can be carried out synchronously. Each unit adopts transactional modeling method, the design cycle is shorter and the simulation speed is 2 ~ 3 orders of magnitude faster than the traditional RTL model. After verification, the software and hardware are translated into the corresponding high-level language and hardware description language. In order to achieve the goal of saving time. The transaction level model of 1553B bus designed in this paper is a part of the laboratory transactional So C verification platform, which can complete the fast verification of the IP core based on 1553B bus. System C language is used for transactional modeling. The modeling standard is the communication between TLM2.0, modules. This paper first introduces the application background of 1553B bus, the present situation of its development and the necessity of modeling it, the mechanism of transaction level modeling using System C, and then puts forward the overall design scheme of 1553B bus model. The design of bus controller interface (BC interface), remote terminal interface (RT interface) and transactional bus channel is completed. After the design of each part of the bus model is finished, the test platform is built and two test schemes are put forward. One is to test the function point to verify the correctness of the function. The second is to test the bus model by exhaustive 16bit instruction word of 1553B bus and evaluate the simulation speed of the model. After a preliminary test, the transactional bus model is mounted on the LEON3 So C verification platform for final test, and a real IP--DES cryptographic algorithm module is mounted on the RT side of the 1553B bus model to complete the verification of the bus model. It is proved that the 1553B bus transaction level model is correct, and the communication with the So C verification platform is successfully completed. Compared with the traditional RTL model, the simulation speed is improved, and it can be used for the fast verification of the 1553B bus IP core.
【學(xué)位授予單位】：哈爾濱工業(yè)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN47
【參考文獻(xiàn)】
相關(guān)期刊論文 前1條
1 唐豪川;祝永新;;基于SystemC的異構(gòu)多核通信模塊設(shè)計(jì)[J];微計(jì)算機(jī)信息;2009年23期
相關(guān)博士學(xué)位論文 前1條
1 浦漢來;SoC存儲(chǔ)子系統(tǒng)系統(tǒng)級(jí)性能優(yōu)化技術(shù)研究[D];東南大學(xué);2006年
相關(guān)碩士學(xué)位論文 前3條
1 馮成;基于FPGA的航電接口板設(shè)計(jì)[D];南京理工大學(xué);2007年
2 何珍珍;1553B總線接口電路存儲(chǔ)器管理控制系統(tǒng)設(shè)計(jì)[D];西安科技大學(xué);2012年
3 王研;1553B總線現(xiàn)場(chǎng)測(cè)試儀的研究及設(shè)計(jì)[D];西安科技大學(xué);2013年
，本文編號(hào)：2346913
本文鏈接：http://sikaile.net/kejilunwen/dianzigongchenglunwen/2346913.html
最近更新
教材專著
