基于SystemC的1553B總線事務(wù)級模型設(shè)計
發(fā)布時間：2018-11-21 12:04
【摘要】：隨著集成電路規(guī)模的不斷增大,電路性能提升的同時也給設(shè)計和驗證工作帶來了新的挑戰(zhàn)。在傳統(tǒng)的超大規(guī)模集成電路的設(shè)計流程中,硬件的設(shè)計與軟件的設(shè)計工作是分開進行的,并且軟件的設(shè)計往往要滯后于硬件,在整合軟硬件時如果想要對設(shè)計進行修改又不得不重新劃分軟硬件的職能,并從頭開始設(shè)計。這就帶來了時間和精力上的浪費。對于驗證而言,使用傳統(tǒng)高級語言的驗證程序與周期精確的硬件描述語言進行混合仿真,速度很慢,往往會導致整個進度的滯后。這在追求產(chǎn)品快速更新?lián)屨际袌龅慕裉焓请y以忍受的。為了解決以上的問題,可以在設(shè)計流程中使用System C語言先進行系統(tǒng)級的設(shè)計,軟硬件的設(shè)計工作可以同步進行。各個單元采用事務(wù)級的建模方法,設(shè)計周期更短并且仿真速度比傳統(tǒng)的RTL模型快2~3個數(shù)量級,通過驗證后再將軟硬件翻譯成對應的高級語言和硬件描述語言,從而達到節(jié)約時間的目的。本文設(shè)計的1553B總線事務(wù)級模型是實驗室事務(wù)級So C驗證平臺的一部分,可以對基于1553B總線的IP核完成快速的驗證工作。采用System C語言進行事務(wù)級的建模,建模標準采用的是TLM2.0,模塊之間的通訊更加規(guī)范。首先介紹1553B總線的應用背景、發(fā)展現(xiàn)狀以及對其進行建模的必要性,利用System C進行事務(wù)級建模的機制,接著提出了1553B總線模型的整體設(shè)計方案,完成總線控制器接口(BC接口)、遠程終端接口(RT接口)和事務(wù)級總線通道的設(shè)計工作。在總線模型的各個部分設(shè)計工作完成后,為其搭建測試平臺并提出兩種測試方案,一是對其功能點進行點對點的測試,驗證功能的正確性,二是采用對1553B總線16bit指令字進行窮舉的方式對總線模型進行全覆蓋測試,評估模型的仿真速度。通過初步的測試后將該事務(wù)級總線模型掛載到LEON3 So C驗證平臺上進行最終的測試,并在1553B總線模型的RT端掛載一個真實的IP——DES密碼算法模塊,完成總線模型的驗證工作。經(jīng)驗證該1553B總線事務(wù)級模型功能實現(xiàn)正確,成功完成了與So C驗證平臺的通信,并且相比于傳統(tǒng)的RTL模型提高了仿真速度,可以用于1553B總線IP核的快速驗證工作。
[Abstract]:With the increasing scale of integrated circuits, the improvement of circuit performance brings new challenges to the design and verification work. In the traditional design flow of VLSI, the design of hardware and software are carried out separately, and the design of software often lags behind that of hardware. When integrating software and hardware, if you want to modify the design, you have to redivide the functions of the software and hardware, and design from scratch. This creates a waste of time and energy. For verification, using traditional high-level language verifier and cycle precise hardware description language for hybrid simulation, the speed is very slow, often lead to the whole progress of the lag. This in the pursuit of rapid product updates to seize the market today is intolerable. In order to solve the above problems, the system level design can be carried out by using System C language in the design process, and the design of software and hardware can be carried out synchronously. Each unit adopts transactional modeling method, the design cycle is shorter and the simulation speed is 2 ~ 3 orders of magnitude faster than the traditional RTL model. After verification, the software and hardware are translated into the corresponding high-level language and hardware description language. In order to achieve the goal of saving time. The transaction level model of 1553B bus designed in this paper is a part of the laboratory transactional So C verification platform, which can complete the fast verification of the IP core based on 1553B bus. System C language is used for transactional modeling. The modeling standard is the communication between TLM2.0, modules. This paper first introduces the application background of 1553B bus, the present situation of its development and the necessity of modeling it, the mechanism of transaction level modeling using System C, and then puts forward the overall design scheme of 1553B bus model. The design of bus controller interface (BC interface), remote terminal interface (RT interface) and transactional bus channel is completed. After the design of each part of the bus model is finished, the test platform is built and two test schemes are put forward. One is to test the function point to verify the correctness of the function. The second is to test the bus model by exhaustive 16bit instruction word of 1553B bus and evaluate the simulation speed of the model. After a preliminary test, the transactional bus model is mounted on the LEON3 So C verification platform for final test, and a real IP--DES cryptographic algorithm module is mounted on the RT side of the 1553B bus model to complete the verification of the bus model. It is proved that the 1553B bus transaction level model is correct, and the communication with the So C verification platform is successfully completed. Compared with the traditional RTL model, the simulation speed is improved, and it can be used for the fast verification of the 1553B bus IP core.
【學位授予單位】：哈爾濱工業(yè)大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN47
本文編號：2346913
[Abstract]:With the increasing scale of integrated circuits, the improvement of circuit performance brings new challenges to the design and verification work. In the traditional design flow of VLSI, the design of hardware and software are carried out separately, and the design of software often lags behind that of hardware. When integrating software and hardware, if you want to modify the design, you have to redivide the functions of the software and hardware, and design from scratch. This creates a waste of time and energy. For verification, using traditional high-level language verifier and cycle precise hardware description language for hybrid simulation, the speed is very slow, often lead to the whole progress of the lag. This in the pursuit of rapid product updates to seize the market today is intolerable. In order to solve the above problems, the system level design can be carried out by using System C language in the design process, and the design of software and hardware can be carried out synchronously. Each unit adopts transactional modeling method, the design cycle is shorter and the simulation speed is 2 ~ 3 orders of magnitude faster than the traditional RTL model. After verification, the software and hardware are translated into the corresponding high-level language and hardware description language. In order to achieve the goal of saving time. The transaction level model of 1553B bus designed in this paper is a part of the laboratory transactional So C verification platform, which can complete the fast verification of the IP core based on 1553B bus. System C language is used for transactional modeling. The modeling standard is the communication between TLM2.0, modules. This paper first introduces the application background of 1553B bus, the present situation of its development and the necessity of modeling it, the mechanism of transaction level modeling using System C, and then puts forward the overall design scheme of 1553B bus model. The design of bus controller interface (BC interface), remote terminal interface (RT interface) and transactional bus channel is completed. After the design of each part of the bus model is finished, the test platform is built and two test schemes are put forward. One is to test the function point to verify the correctness of the function. The second is to test the bus model by exhaustive 16bit instruction word of 1553B bus and evaluate the simulation speed of the model. After a preliminary test, the transactional bus model is mounted on the LEON3 So C verification platform for final test, and a real IP--DES cryptographic algorithm module is mounted on the RT side of the 1553B bus model to complete the verification of the bus model. It is proved that the 1553B bus transaction level model is correct, and the communication with the So C verification platform is successfully completed. Compared with the traditional RTL model, the simulation speed is improved, and it can be used for the fast verification of the 1553B bus IP core.
【學位授予單位】：哈爾濱工業(yè)大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN47
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