異構多核系統(tǒng)調試技術的研究與實現(xiàn)
發(fā)布時間：2018-11-20 18:42
【摘要】：隨著半導體制造工藝的快速發(fā)展以及集成電路設計技術的不斷提高,傳統(tǒng)的單核SoC架構已經(jīng)無法滿足日益增長的性能需求,多核SoC技術應運而生。相較于同構多核系統(tǒng),異構多核系統(tǒng)能夠實現(xiàn)資源的最優(yōu)化配置,在處理復雜特定任務時具有更大的優(yōu)勢。然而,異構多核系統(tǒng)的出現(xiàn),導致軟硬件設計的正確性驗證更加困難,沒有硬件支持的調試技術已經(jīng)無法勝任這些復雜的應用。因此,在芯片中采用可調試性設計逐漸成為一種提高芯片調試效率的重要手段,并得到學術界和工業(yè)界的廣泛研究。本文針對上述問題,開展了異構多核系統(tǒng)調試技術的相關研究。論文的主要工作如下：首先,基于課題組設計完成的一款異構多核系統(tǒng),設計并實現(xiàn)了一種可配置可裁剪的可調試性模型,為目標系統(tǒng)芯片的生產(chǎn)及實際應用提供有力的支持�？烧{試性模型包括片上調試架構和上位機軟件兩部分,本文的工作重點是目標系統(tǒng)可調試性設計的硬件部分,即片上調試架構的設計與實現(xiàn)。其次,對片上調試架構中調試探測器DP的設計進行深入研究,詳細分析了目標系統(tǒng)中不同資源節(jié)點的調試方案以及相應DP的配置,證明了DP設計的靈活性,同時完成了目標系統(tǒng)中各類資源節(jié)點DP模塊的電路設計工作。此外,還給出了各DP在FPGA上實現(xiàn)的面積開銷,論述了本設計的有效性。最后,將DP模塊集成于目標系統(tǒng)中,從RTL級和FPGA兩個層次驗證了本文設計的DP功能的正確性。此外,通過一個分步調試的應用實例,論述了本文的可調試性設計模型可以通過不同模式的任意組合,快速定位錯誤所在,有效地支持目標系統(tǒng)的調試工作。本文實現(xiàn)的可調試性設計模型在對目標系統(tǒng)的調試控制方面具有如下特點：(1)采取“離線”調試方案,即預先設定斷點或觸發(fā)點,待系統(tǒng)執(zhí)行觸發(fā)調試后,暫停原執(zhí)行過程進入調試態(tài),獲取相關調試數(shù)據(jù)之后再恢復系統(tǒng)運行。(2)提供五種不同的調試模式以滿足目標系統(tǒng)實際應用的調試需求,每次可以根據(jù)需選擇一種模式生成調試控制命令。(3)調試單元采用模塊化設計,對其作相應的功能裁剪,即可實現(xiàn)針對系統(tǒng)中不同資源節(jié)點的可調試性設計。(4)調試單元具有可配置性,通過配置各控制寄存器,靈活地設置斷點或觀察點。
[Abstract]:With the rapid development of semiconductor manufacturing process and the continuous improvement of integrated circuit design technology, the traditional single-core SoC architecture can no longer meet the increasing performance requirements, and the multi-core SoC technology emerges as the times require. Compared with isomorphic multicore systems, heterogeneous multicore systems can achieve optimal allocation of resources and have greater advantages in dealing with complex and specific tasks. However, due to the emergence of heterogeneous multi-core systems, it is more difficult to verify the correctness of hardware and software design, and the debugging technology without hardware support can not be used in these complex applications. Therefore, the use of debug design in chips has gradually become an important means to improve the efficiency of chip debugging, and has been widely studied by academia and industry. In order to solve the above problems, this paper studies the debugging technology of heterogeneous multi-core system. The main work of this paper is as follows: firstly, based on a heterogeneous multi-core system designed by the research group, a configurable and tailor-made debug model is designed and implemented, which provides a powerful support for the production and practical application of the target system chip. The debug model includes two parts: on-chip debugging architecture and host computer software. The emphasis of this paper is the hardware part of the debug design of the target system, that is, the design and implementation of the on-chip debugging architecture. Secondly, the design of debug detector DP in the on-chip debugging architecture is studied, and the debugging scheme of different resource nodes in the target system and the configuration of corresponding DP are analyzed in detail, which proves the flexibility of DP design. At the same time, the circuit design of various resource node DP modules in the target system is completed. In addition, the area overhead realized by DP on FPGA is given, and the effectiveness of this design is discussed. Finally, the DP module is integrated into the target system, and the correctness of the DP function designed in this paper is verified from the RTL level and the FPGA level. In addition, through an application example of step debugging, it is discussed that the debugging design model of this paper can quickly locate the error by any combination of different modes, and effectively support the debugging work of the target system. The Debuggability Design Model realized in this paper has the following characteristics in debugging and controlling the target system: (1) the off-line debugging scheme is adopted, that is, the breakpoint or trigger point is set in advance, and after the system executes the trigger debugging, Pause the original execution process into debugging state, obtain relevant debugging data before resuming the system. (2) provide five different debugging modes to meet the debugging needs of the actual application of the target system. According to the need to select a mode to generate debug control commands. (3) the debugging unit is designed by modularization, and the corresponding function is clipped. Debuggability design for different resource nodes in the system can be realized. (4) Debug unit is configurable and can set breakpoint or observation point flexibly by configuring each control register.
【學位授予單位】：合肥工業(yè)大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN402
本文編號：2345670
[Abstract]:With the rapid development of semiconductor manufacturing process and the continuous improvement of integrated circuit design technology, the traditional single-core SoC architecture can no longer meet the increasing performance requirements, and the multi-core SoC technology emerges as the times require. Compared with isomorphic multicore systems, heterogeneous multicore systems can achieve optimal allocation of resources and have greater advantages in dealing with complex and specific tasks. However, due to the emergence of heterogeneous multi-core systems, it is more difficult to verify the correctness of hardware and software design, and the debugging technology without hardware support can not be used in these complex applications. Therefore, the use of debug design in chips has gradually become an important means to improve the efficiency of chip debugging, and has been widely studied by academia and industry. In order to solve the above problems, this paper studies the debugging technology of heterogeneous multi-core system. The main work of this paper is as follows: firstly, based on a heterogeneous multi-core system designed by the research group, a configurable and tailor-made debug model is designed and implemented, which provides a powerful support for the production and practical application of the target system chip. The debug model includes two parts: on-chip debugging architecture and host computer software. The emphasis of this paper is the hardware part of the debug design of the target system, that is, the design and implementation of the on-chip debugging architecture. Secondly, the design of debug detector DP in the on-chip debugging architecture is studied, and the debugging scheme of different resource nodes in the target system and the configuration of corresponding DP are analyzed in detail, which proves the flexibility of DP design. At the same time, the circuit design of various resource node DP modules in the target system is completed. In addition, the area overhead realized by DP on FPGA is given, and the effectiveness of this design is discussed. Finally, the DP module is integrated into the target system, and the correctness of the DP function designed in this paper is verified from the RTL level and the FPGA level. In addition, through an application example of step debugging, it is discussed that the debugging design model of this paper can quickly locate the error by any combination of different modes, and effectively support the debugging work of the target system. The Debuggability Design Model realized in this paper has the following characteristics in debugging and controlling the target system: (1) the off-line debugging scheme is adopted, that is, the breakpoint or trigger point is set in advance, and after the system executes the trigger debugging, Pause the original execution process into debugging state, obtain relevant debugging data before resuming the system. (2) provide five different debugging modes to meet the debugging needs of the actual application of the target system. According to the need to select a mode to generate debug control commands. (3) the debugging unit is designed by modularization, and the corresponding function is clipped. Debuggability design for different resource nodes in the system can be realized. (4) Debug unit is configurable and can set breakpoint or observation point flexibly by configuring each control register.
【學位授予單位】：合肥工業(yè)大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN402
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