【摘要】：隨著半導(dǎo)體制造工藝的快速發(fā)展以及集成電路設(shè)計(jì)技術(shù)的不斷提高,傳統(tǒng)的單核SoC架構(gòu)已經(jīng)無(wú)法滿足日益增長(zhǎng)的性能需求,多核SoC技術(shù)應(yīng)運(yùn)而生。相較于同構(gòu)多核系統(tǒng),異構(gòu)多核系統(tǒng)能夠?qū)崿F(xiàn)資源的最優(yōu)化配置,在處理復(fù)雜特定任務(wù)時(shí)具有更大的優(yōu)勢(shì)。然而,異構(gòu)多核系統(tǒng)的出現(xiàn),導(dǎo)致軟硬件設(shè)計(jì)的正確性驗(yàn)證更加困難,沒(méi)有硬件支持的調(diào)試技術(shù)已經(jīng)無(wú)法勝任這些復(fù)雜的應(yīng)用。因此,在芯片中采用可調(diào)試性設(shè)計(jì)逐漸成為一種提高芯片調(diào)試效率的重要手段,并得到學(xué)術(shù)界和工業(yè)界的廣泛研究。本文針對(duì)上述問(wèn)題,開(kāi)展了異構(gòu)多核系統(tǒng)調(diào)試技術(shù)的相關(guān)研究。論文的主要工作如下：首先,基于課題組設(shè)計(jì)完成的一款異構(gòu)多核系統(tǒng),設(shè)計(jì)并實(shí)現(xiàn)了一種可配置可裁剪的可調(diào)試性模型,為目標(biāo)系統(tǒng)芯片的生產(chǎn)及實(shí)際應(yīng)用提供有力的支持�？烧{(diào)試性模型包括片上調(diào)試架構(gòu)和上位機(jī)軟件兩部分,本文的工作重點(diǎn)是目標(biāo)系統(tǒng)可調(diào)試性設(shè)計(jì)的硬件部分,即片上調(diào)試架構(gòu)的設(shè)計(jì)與實(shí)現(xiàn)。其次,對(duì)片上調(diào)試架構(gòu)中調(diào)試探測(cè)器DP的設(shè)計(jì)進(jìn)行深入研究,詳細(xì)分析了目標(biāo)系統(tǒng)中不同資源節(jié)點(diǎn)的調(diào)試方案以及相應(yīng)DP的配置,證明了DP設(shè)計(jì)的靈活性,同時(shí)完成了目標(biāo)系統(tǒng)中各類(lèi)資源節(jié)點(diǎn)DP模塊的電路設(shè)計(jì)工作。此外,還給出了各DP在FPGA上實(shí)現(xiàn)的面積開(kāi)銷(xiāo),論述了本設(shè)計(jì)的有效性。最后,將DP模塊集成于目標(biāo)系統(tǒng)中,從RTL級(jí)和FPGA兩個(gè)層次驗(yàn)證了本文設(shè)計(jì)的DP功能的正確性。此外,通過(guò)一個(gè)分步調(diào)試的應(yīng)用實(shí)例,論述了本文的可調(diào)試性設(shè)計(jì)模型可以通過(guò)不同模式的任意組合,快速定位錯(cuò)誤所在,有效地支持目標(biāo)系統(tǒng)的調(diào)試工作。本文實(shí)現(xiàn)的可調(diào)試性設(shè)計(jì)模型在對(duì)目標(biāo)系統(tǒng)的調(diào)試控制方面具有如下特點(diǎn)：(1)采取“離線”調(diào)試方案,即預(yù)先設(shè)定斷點(diǎn)或觸發(fā)點(diǎn),待系統(tǒng)執(zhí)行觸發(fā)調(diào)試后,暫停原執(zhí)行過(guò)程進(jìn)入調(diào)試態(tài),獲取相關(guān)調(diào)試數(shù)據(jù)之后再恢復(fù)系統(tǒng)運(yùn)行。(2)提供五種不同的調(diào)試模式以滿足目標(biāo)系統(tǒng)實(shí)際應(yīng)用的調(diào)試需求,每次可以根據(jù)需選擇一種模式生成調(diào)試控制命令。(3)調(diào)試單元采用模塊化設(shè)計(jì),對(duì)其作相應(yīng)的功能裁剪,即可實(shí)現(xiàn)針對(duì)系統(tǒng)中不同資源節(jié)點(diǎn)的可調(diào)試性設(shè)計(jì)。(4)調(diào)試單元具有可配置性,通過(guò)配置各控制寄存器,靈活地設(shè)置斷點(diǎn)或觀察點(diǎn)。
[Abstract]:With the rapid development of semiconductor manufacturing process and the continuous improvement of integrated circuit design technology, the traditional single-core SoC architecture can no longer meet the increasing performance requirements, and the multi-core SoC technology emerges as the times require. Compared with isomorphic multicore systems, heterogeneous multicore systems can achieve optimal allocation of resources and have greater advantages in dealing with complex and specific tasks. However, due to the emergence of heterogeneous multi-core systems, it is more difficult to verify the correctness of hardware and software design, and the debugging technology without hardware support can not be used in these complex applications. Therefore, the use of debug design in chips has gradually become an important means to improve the efficiency of chip debugging, and has been widely studied by academia and industry. In order to solve the above problems, this paper studies the debugging technology of heterogeneous multi-core system. The main work of this paper is as follows: firstly, based on a heterogeneous multi-core system designed by the research group, a configurable and tailor-made debug model is designed and implemented, which provides a powerful support for the production and practical application of the target system chip. The debug model includes two parts: on-chip debugging architecture and host computer software. The emphasis of this paper is the hardware part of the debug design of the target system, that is, the design and implementation of the on-chip debugging architecture. Secondly, the design of debug detector DP in the on-chip debugging architecture is studied, and the debugging scheme of different resource nodes in the target system and the configuration of corresponding DP are analyzed in detail, which proves the flexibility of DP design. At the same time, the circuit design of various resource node DP modules in the target system is completed. In addition, the area overhead realized by DP on FPGA is given, and the effectiveness of this design is discussed. Finally, the DP module is integrated into the target system, and the correctness of the DP function designed in this paper is verified from the RTL level and the FPGA level. In addition, through an application example of step debugging, it is discussed that the debugging design model of this paper can quickly locate the error by any combination of different modes, and effectively support the debugging work of the target system. The Debuggability Design Model realized in this paper has the following characteristics in debugging and controlling the target system: (1) the off-line debugging scheme is adopted, that is, the breakpoint or trigger point is set in advance, and after the system executes the trigger debugging, Pause the original execution process into debugging state, obtain relevant debugging data before resuming the system. (2) provide five different debugging modes to meet the debugging needs of the actual application of the target system. According to the need to select a mode to generate debug control commands. (3) the debugging unit is designed by modularization, and the corresponding function is clipped. Debuggability design for different resource nodes in the system can be realized. (4) Debug unit is configurable and can set breakpoint or observation point flexibly by configuring each control register.
【學(xué)位授予單位】：合肥工業(yè)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類(lèi)號(hào)】：TN402

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