基于FPGA的IIC在線測試系統(tǒng)
發(fā)布時間：2018-11-20 16:40
【摘要】：隨著半導(dǎo)體工藝設(shè)計規(guī)模的不斷增加,芯片的集成度和復(fù)雜度不斷增大,芯片的測試變得復(fù)雜而耗時,這將嚴(yán)重阻礙半導(dǎo)體行業(yè)的發(fā)展。在集成電路領(lǐng)域中,芯片的測試占據(jù)整個芯片開發(fā)周期的70%以上。因此,快速精確實現(xiàn)對芯片的測試己成為我們急需解決的問題。傳統(tǒng)的芯片測試主要依靠示波器和信號發(fā)生器等測試儀器,通過人手工實現(xiàn)對芯片的各個接口進行測試,市場上的示波器和信號發(fā)生器并不是針對芯片測試領(lǐng)域而設(shè)計的,因而這種測試方法測試項單一,測試流程復(fù)雜、耗時�，F(xiàn)有的EDA驗證軟件的驗證功能往往很局限,根本無法滿足大規(guī)模的集成電路測試要求。因此,本文提出的是一種基于FPGA平臺的IIC在線測試系統(tǒng),該系統(tǒng)率先通過設(shè)計碼型發(fā)送器與碼型接收器實現(xiàn)對芯片IIC總線接口的測試,該系統(tǒng)的測試項達二十多項,測試項全面,并且測試的工作量大大減少。整個測試流程在PC機通過使用TCL腳本控制系統(tǒng)工作,實現(xiàn)測試全自動化,在線得到測試結(jié)果。該系統(tǒng)測試準(zhǔn)確可靠并且完全擺脫對示波器、信號發(fā)生器等測試儀器的依懶,不僅能夠?qū)崿F(xiàn)IIC波形的重現(xiàn),并且能夠得到精確的測試結(jié)果。本文通過對5560X芯片的IIC接口的成功測試,證實了本系統(tǒng)的準(zhǔn)確性和可行性。本文目前雖然只支持IIC接口的測試,但在其設(shè)計初期己將各類總線的測試考慮在內(nèi),如SPI、LOCALBUS和MDIO總線等。本系統(tǒng)具很強的擴展性,并且設(shè)計思路新穎,系統(tǒng)在設(shè)計初期并沒有將各類總線特殊化,而是將各類總線根據(jù)其通信的信號線數(shù)進行劃分,采用碼型多變,硬件設(shè)計模塊少變的方法實現(xiàn)對各類總線的測試。本系統(tǒng)的提出,將有效解決了芯片驗證領(lǐng)域中操作過于復(fù)雜、測試的時間過長的問題,很具實用前景。
[Abstract]:With the increasing scale of semiconductor process planning and the increasing integration and complexity of chips, the testing of chips becomes complex and time-consuming, which will seriously hinder the development of semiconductor industry. In the field of integrated circuits, chip testing accounts for more than 70% of the whole chip development cycle. Therefore, the rapid and accurate implementation of chip testing has become a problem we urgently need to solve. The traditional chip test mainly depends on the oscilloscope and signal generator and other testing instruments. The interface of the chip is tested by human hand. The oscilloscope and signal generator in the market are not designed for the field of chip testing. Therefore, the test method is simple, complex and time-consuming. The verification function of the existing EDA verification software is often very limited and can not meet the requirements of large-scale integrated circuit testing. Therefore, this paper presents a IIC on-line test system based on FPGA platform. The system is the first to test the chip IIC bus interface by designing the code transmitter and the code receiver. The test items of the system reach more than 20 items. The test items are comprehensive and the workload of the tests is greatly reduced. The whole testing process works in the PC machine by using TCL script control system to realize the full automation of the test and get the test results online. The system is accurate and reliable and can completely get rid of the idleness of oscilloscope signal generator and other test instruments. It can not only realize the IIC waveform reproduction but also get accurate test results. The accuracy and feasibility of this system are verified by the successful test of IIC interface of 5560X chip. Although this paper only supports the test of IIC interface, the test of all kinds of buses, such as SPI,LOCALBUS and MDIO bus, has been taken into account at the beginning of its design. This system has very strong expansibility, and the design idea is novel, the system does not specialized all kinds of buses at the beginning of the design, but divides the various kinds of buses according to the number of the signal lines of its communication, adopts the code type changeable, The method of less change of hardware design module realizes the test of all kinds of buses. This system will effectively solve the problem of too complicated operation and too long test time in the field of chip verification.
【學(xué)位授予單位】：廣東工業(yè)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN407
本文編號：2345425
[Abstract]:With the increasing scale of semiconductor process planning and the increasing integration and complexity of chips, the testing of chips becomes complex and time-consuming, which will seriously hinder the development of semiconductor industry. In the field of integrated circuits, chip testing accounts for more than 70% of the whole chip development cycle. Therefore, the rapid and accurate implementation of chip testing has become a problem we urgently need to solve. The traditional chip test mainly depends on the oscilloscope and signal generator and other testing instruments. The interface of the chip is tested by human hand. The oscilloscope and signal generator in the market are not designed for the field of chip testing. Therefore, the test method is simple, complex and time-consuming. The verification function of the existing EDA verification software is often very limited and can not meet the requirements of large-scale integrated circuit testing. Therefore, this paper presents a IIC on-line test system based on FPGA platform. The system is the first to test the chip IIC bus interface by designing the code transmitter and the code receiver. The test items of the system reach more than 20 items. The test items are comprehensive and the workload of the tests is greatly reduced. The whole testing process works in the PC machine by using TCL script control system to realize the full automation of the test and get the test results online. The system is accurate and reliable and can completely get rid of the idleness of oscilloscope signal generator and other test instruments. It can not only realize the IIC waveform reproduction but also get accurate test results. The accuracy and feasibility of this system are verified by the successful test of IIC interface of 5560X chip. Although this paper only supports the test of IIC interface, the test of all kinds of buses, such as SPI,LOCALBUS and MDIO bus, has been taken into account at the beginning of its design. This system has very strong expansibility, and the design idea is novel, the system does not specialized all kinds of buses at the beginning of the design, but divides the various kinds of buses according to the number of the signal lines of its communication, adopts the code type changeable, The method of less change of hardware design module realizes the test of all kinds of buses. This system will effectively solve the problem of too complicated operation and too long test time in the field of chip verification.
【學(xué)位授予單位】：廣東工業(yè)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN407
【參考文獻】
相關(guān)期刊論文 前4條
1 陳遠華;劉文華;宋強;;基于FPGA的級聯(lián)逆變器直接PWM發(fā)生器[J];電力系統(tǒng)自動化;2006年09期
2 劉祥遠;陳書明;;一種高性能的異步FIFO結(jié)構(gòu)[J];電子學(xué)報;2007年11期
3 陳剛;陳旭;陳天翔;龔國良;邊f(xié)3;魯華祥;;基于FPGA的微電流傳感器相位差自校正系統(tǒng)[J];電力系統(tǒng)自動化;2013年20期
4 陳光建;賈金玲;;基于單片機的I~2C總線系統(tǒng)設(shè)計[J];儀器儀表學(xué)報;2006年S3期
相關(guān)碩士學(xué)位論文 前3條
1 黃澤利;基于TMS320DM642的視頻處理系統(tǒng)設(shè)計及算法研究[D];電子科技大學(xué);2007年
2 夏雷;基于TCL語言的系統(tǒng)配置自動化測試腳本設(shè)計與實施[D];北京郵電大學(xué);2007年
3 方學(xué)南;基于FPGA的芯片自動測試平臺的研究與實現(xiàn)[D];華南理工大學(xué);2013年
，本文編號：2345425
本文鏈接：http://sikaile.net/kejilunwen/dianzigongchenglunwen/2345425.html
最近更新
教材專著
