基于OR1200的SoC無(wú)線程序加載系統(tǒng)設(shè)計(jì)與驗(yàn)證
發(fā)布時(shí)間：2018-11-11 08:01
【摘要】：SoC(System-on-chip)是指在一個(gè)芯片上集成完整的系統(tǒng),也是現(xiàn)在運(yùn)用很廣的一種芯片設(shè)計(jì)方法之一。SoC設(shè)計(jì)不是以功能電路為基礎(chǔ)的技術(shù),而是以IP核為基礎(chǔ)搭建系統(tǒng),實(shí)現(xiàn)IP核的復(fù)用。這樣能提高工作效率、節(jié)約成本、增加系統(tǒng)功能、減少出錯(cuò)率等。常見(jiàn)的SoC系統(tǒng)一般包括處理器、總線、存儲(chǔ)模塊、時(shí)鐘模塊和外設(shè)等。對(duì)于SoC設(shè)計(jì)來(lái)說(shuō),搭好環(huán)境后,還得有相應(yīng)的一套IDE開(kāi)發(fā)工具,包括裝有配套開(kāi)發(fā)環(huán)境的PC,電路板和連接線。開(kāi)發(fā)完成后應(yīng)用于嵌入式領(lǐng)域,一般很難支持二次開(kāi)發(fā)�；蛘咧С侄伍_(kāi)發(fā),但是受帶開(kāi)發(fā)環(huán)境的PC終端、電路板、連接線等條件的約束很不方便。因此,本論文中提出一種基于OR1200的無(wú)線智能程序加載SoC設(shè)計(jì)方案,使得芯片能方便的實(shí)現(xiàn)二次開(kāi)發(fā),擺脫帶開(kāi)發(fā)環(huán)境的PC終端、開(kāi)發(fā)板、連接線等條件的約束,增加芯片的利用率,簡(jiǎn)化二次開(kāi)發(fā)流程。其中OR1200是開(kāi)源項(xiàng)目OpenRISC項(xiàng)目的一個(gè)子項(xiàng)目,采用的是Harvard結(jié)構(gòu),是32位的RISC處理器,具有免費(fèi)、開(kāi)源、簡(jiǎn)單、低功耗和可擴(kuò)展等優(yōu)點(diǎn)。性能上來(lái)說(shuō)相當(dāng)于ARM9的性能。本文所述基于OR1200的SoC程序加載系統(tǒng)中,它至少包括處理器、只讀存儲(chǔ)器、總線仲裁模塊、串行外設(shè)接口、內(nèi)存模塊、通用異步收發(fā)傳輸器、時(shí)鐘模塊等。Wishbone總線仲裁采用輪循機(jī)制實(shí)現(xiàn)主設(shè)備與從設(shè)備之間的訪問(wèn)。此文改變了傳統(tǒng)的把一個(gè)程序存儲(chǔ)在flash中,當(dāng)燒錄下一個(gè)程序時(shí)就會(huì)覆蓋上一個(gè)程序的做法,而把flash劃分成三個(gè)程序區(qū)。燒錄flash時(shí),把不同的程序放在不同的程序區(qū)。當(dāng)從SPI flash啟動(dòng)時(shí),程序指針首先指向只讀存儲(chǔ)器ROM里面的Bootload區(qū),以完成程序從flash拷貝到內(nèi)存,再?gòu)膬?nèi)存開(kāi)始執(zhí)行指令,實(shí)現(xiàn)系統(tǒng)的自啟動(dòng)。此外,本文設(shè)計(jì)在此基礎(chǔ)上增加了Bootload的功能,即不僅能完成程序的拷貝,還能監(jiān)測(cè)串口,根據(jù)收到的命令選擇一個(gè)程序區(qū)的程序拷貝到內(nèi)存。使得芯片封裝好之后,無(wú)需接線,無(wú)需相應(yīng)的IDE軟件來(lái)加載程序,通過(guò)手機(jī)或帶有藍(lán)牙模塊的終端就可以加載不同的程序,此設(shè)計(jì)在智能終端領(lǐng)域能有很好的應(yīng)用�；赟oC的無(wú)線智能程序加載方法步驟如下:搭建SoC系統(tǒng);將加載啟動(dòng)代碼燒錄至只讀存儲(chǔ)器中;將flash存儲(chǔ)器分區(qū)并加載不同的程序;初始化串行外設(shè)接口和通用異步收發(fā)傳輸器,從flash存儲(chǔ)器中選擇相應(yīng)程序區(qū)實(shí)現(xiàn)程序到內(nèi)存模塊的拷貝;執(zhí)行跳轉(zhuǎn)命令,將處理器指向內(nèi)存模塊的起始位置,實(shí)現(xiàn)系統(tǒng)的自啟動(dòng)。通過(guò)帶藍(lán)牙功能的終端發(fā)送不同的命令即可選擇flash程序區(qū)中不同的程序加載到內(nèi)存模塊,通過(guò)無(wú)線控制實(shí)現(xiàn)不同程序的加載。本論文中不僅描述了一種基于OR1200的SoC程序加載方案,還實(shí)現(xiàn)了此方案的設(shè)計(jì),經(jīng)過(guò)EDA工具綜合和仿真后,在Xilinx開(kāi)發(fā)板上進(jìn)行下板測(cè)試。
[Abstract]:SoC (System-on-chip) refers to the integration of a complete system on a chip, which is also one of the most widely used chip design methods. SoC design is not based on functional circuit technology, but based on IP core. The reuse of IP core is realized. This can improve working efficiency, save cost, increase system function, reduce error rate and so on. Common SoC systems generally include processors, buses, storage modules, clock modules and peripherals. For the SoC design, there must be a set of IDE development tools, including the PC, circuit board and connection wire, which are equipped with the supporting development environment. After the development is completed, it is difficult to support the secondary development when it is applied to the embedded field. Or support secondary development, but with the development environment of PC terminals, circuit boards, connectors and other constraints are very inconvenient. Therefore, this paper proposes a wireless intelligent program loading SoC design scheme based on OR1200, which makes the chip realize secondary development conveniently and get rid of the constraints of PC terminal, development board, connection line and so on. Increase the utilization rate of the chip, simplify the secondary development process. OR1200 is a subproject of the open source project OpenRISC, which uses Harvard structure and is a 32-bit RISC processor with the advantages of free, open source, simple, low power consumption and extensibility. Performance is equivalent to that of ARM9. In the SoC program loading system based on OR1200, it includes at least processor, read-only memory, bus arbitration module, serial peripheral interface, memory module, universal asynchronous transceiver, etc. Clock module and so on. Wishbone bus arbitration uses the wheel-based mechanism to achieve access between master and slave devices. This paper changes the traditional method of storing a program in flash, which overwrites a program when the next program is burned, and divides flash into three program regions. When burning flash, put different programs in different program areas. When starting from SPI flash, the program pointer first points to the Bootload area in the read-only memory (ROM) to complete the program copying from flash to memory, and then executes instructions from memory to realize the self-start of the system. In addition, this paper adds the function of Bootload, which can not only complete the copy of the program, but also monitor the serial port, and select a program copy to the memory according to the commands received. After the chip encapsulation, no wiring, no corresponding IDE software to load the program, through the mobile phone or the terminal with Bluetooth module can load different programs, this design can be used in the field of smart terminals. The method of wireless intelligent program loading based on SoC is as follows: build SoC system; burn load start code into read-only memory; partition flash memory and load different programs; The serial peripheral interface and the universal asynchronous transceiver are initialized, and the corresponding program area is selected from the flash memory to realize the copy of the program to the memory module. Execute jump command, point the processor to the starting position of the memory module, realize the self-start of the system. Different programs in the flash program area can be selected to load into the memory module by sending different commands from the terminal with Bluetooth function, and different programs can be loaded by wireless control. In this paper, not only a SoC program loading scheme based on OR1200 is described, but also the design of this scheme is realized. After the EDA tool synthesis and simulation, the next board test is carried out on the Xilinx development board.
【學(xué)位授予單位】：湘潭大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類(lèi)號(hào)】：TN402
本文編號(hào)：2324254
[Abstract]:SoC (System-on-chip) refers to the integration of a complete system on a chip, which is also one of the most widely used chip design methods. SoC design is not based on functional circuit technology, but based on IP core. The reuse of IP core is realized. This can improve working efficiency, save cost, increase system function, reduce error rate and so on. Common SoC systems generally include processors, buses, storage modules, clock modules and peripherals. For the SoC design, there must be a set of IDE development tools, including the PC, circuit board and connection wire, which are equipped with the supporting development environment. After the development is completed, it is difficult to support the secondary development when it is applied to the embedded field. Or support secondary development, but with the development environment of PC terminals, circuit boards, connectors and other constraints are very inconvenient. Therefore, this paper proposes a wireless intelligent program loading SoC design scheme based on OR1200, which makes the chip realize secondary development conveniently and get rid of the constraints of PC terminal, development board, connection line and so on. Increase the utilization rate of the chip, simplify the secondary development process. OR1200 is a subproject of the open source project OpenRISC, which uses Harvard structure and is a 32-bit RISC processor with the advantages of free, open source, simple, low power consumption and extensibility. Performance is equivalent to that of ARM9. In the SoC program loading system based on OR1200, it includes at least processor, read-only memory, bus arbitration module, serial peripheral interface, memory module, universal asynchronous transceiver, etc. Clock module and so on. Wishbone bus arbitration uses the wheel-based mechanism to achieve access between master and slave devices. This paper changes the traditional method of storing a program in flash, which overwrites a program when the next program is burned, and divides flash into three program regions. When burning flash, put different programs in different program areas. When starting from SPI flash, the program pointer first points to the Bootload area in the read-only memory (ROM) to complete the program copying from flash to memory, and then executes instructions from memory to realize the self-start of the system. In addition, this paper adds the function of Bootload, which can not only complete the copy of the program, but also monitor the serial port, and select a program copy to the memory according to the commands received. After the chip encapsulation, no wiring, no corresponding IDE software to load the program, through the mobile phone or the terminal with Bluetooth module can load different programs, this design can be used in the field of smart terminals. The method of wireless intelligent program loading based on SoC is as follows: build SoC system; burn load start code into read-only memory; partition flash memory and load different programs; The serial peripheral interface and the universal asynchronous transceiver are initialized, and the corresponding program area is selected from the flash memory to realize the copy of the program to the memory module. Execute jump command, point the processor to the starting position of the memory module, realize the self-start of the system. Different programs in the flash program area can be selected to load into the memory module by sending different commands from the terminal with Bluetooth function, and different programs can be loaded by wireless control. In this paper, not only a SoC program loading scheme based on OR1200 is described, but also the design of this scheme is realized. After the EDA tool synthesis and simulation, the next board test is carried out on the Xilinx development board.
【學(xué)位授予單位】：湘潭大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類(lèi)號(hào)】：TN402
【參考文獻(xiàn)】
相關(guān)碩士學(xué)位論文 前2條
1 彭章超;基于Leon3處理器SoC低功耗設(shè)計(jì)研究[D];合肥工業(yè)大學(xué);2007年
2 劉凱;OpenRISC1200處理器的研究和驗(yàn)證[D];西安電子科技大學(xué);2007年
，本文編號(hào)：2324254
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