面向退化效應(yīng)的組合電路測試通路選擇算法研究
發(fā)布時間：2018-11-07 16:13
【摘要】：測試在集成電路的設(shè)計、生產(chǎn)和制造過程中都扮演著十分重要的作用。對于組合邏輯電路,需要對其內(nèi)部各條通路上的時延進行測試,判斷電路是否滿足時序要求。然而隨著電路規(guī)模的不斷增大,電路中通路的數(shù)量也急劇增長,難以對全部通路進行時延測試,需要在電路所有通路中選擇出延遲最大的關(guān)鍵通路,通過檢測關(guān)鍵通路的延時情況對電路時序狀態(tài)給出評價。然而隨著集成電路特征尺寸的降低和電路結(jié)構(gòu)的日益復(fù)雜,退化效應(yīng)對電路的影響越來越大。退化效應(yīng)對電路內(nèi)各門單元器件的時延情況產(chǎn)生影響,從而影響電路中每條通路上的時延,進而造成在電路生命周期中的不同時刻存在不同的關(guān)鍵通路。因此本文重點分析退化效應(yīng)對組合電路時序造成的影響,根據(jù)電路延遲的變化情況,自適應(yīng)的選擇合適的關(guān)鍵通路進行時延測試,從而提高關(guān)鍵通路選擇的準確性和時延測試的有效性。本文將組合電路退化行為與時延測試通路進行結(jié)合,解決了在退化效應(yīng)影響下的時延測試通路的搜尋問題。從典型退化效應(yīng)機理研究出發(fā),在分析組合電路內(nèi)基本門單元的退化行為的基礎(chǔ)上,研究門單元內(nèi)退化與時延變化的關(guān)系,建立電路內(nèi)門單元時延變化與退化效應(yīng)的關(guān)系。以此為基礎(chǔ),利用拓撲圖思想對電路結(jié)構(gòu)進行建模,獲取電路內(nèi)各器件單元的互聯(lián)關(guān)系,進而建立組合電路測試通路選擇問題的數(shù)學模型。在獲取的時延信息、老化時延信息以及互聯(lián)信息的基礎(chǔ)上,采取貪婪算法中的深度優(yōu)先搜索算法完成對電路關(guān)鍵通路的搜索工作,驗證了在電路生命周期內(nèi),關(guān)鍵通路會由于退化效應(yīng)的影響而發(fā)生變化。為了解決深度優(yōu)先搜索算法在大規(guī)模電路測試通路選擇中搜索效率低、速度慢的問題,本文利用蟻群算法,在盡可能保證通路搜索準確率的條件下提高關(guān)鍵通路的搜索效率。實驗結(jié)果表明,兩種算法都能夠完成退化效應(yīng)下組合電路時延測試的關(guān)鍵通路搜索,并且蟻群優(yōu)化算法在一定程度上,提高了在考慮退化效應(yīng)下的關(guān)鍵通路搜尋的效率。
[Abstract]:Testing plays an important role in the design, production and manufacture of integrated circuits. For combinational logic circuits, it is necessary to test the time delay in each path to determine whether the circuit meets the timing requirements. However, with the increasing of circuit scale, the number of paths in the circuit increases rapidly, so it is difficult to test the delay of all the paths, so it is necessary to select the key path with the largest delay in all the circuit paths. The timing state of the circuit is evaluated by detecting the delay of the critical path. However, with the decreasing of the feature size and the increasing complexity of the circuit structure, the degradation effect is becoming more and more important. The degradation effect has an effect on the delay of each gate element in the circuit, thus affecting the delay on each path in the circuit, which leads to the existence of different critical paths at different times in the circuit life cycle. Therefore, this paper focuses on analyzing the effect of degradation effect on the timing of combinational circuits. According to the variation of circuit delay, we adaptively select the appropriate key path to test the time delay. In order to improve the accuracy of critical path selection and the effectiveness of delay testing. In this paper, the degradation behavior of combinational circuits is combined with the delay test path to solve the problem of searching the delay test path under the influence of degradation effect. Based on the analysis of the degradation behavior of the basic gate cells in the combinational circuits, the relationship between the degradation and the delay changes in the gate cells is studied, and the relationship between the delay changes and the degradation effects of the gate cells in the circuit is established based on the study of the mechanism of the typical degradation effect. On this basis, the topology idea is used to model the circuit structure, to obtain the interconnection of each device unit in the circuit, and then to establish the mathematical model of the test path selection problem of the combinational circuit. On the basis of the acquired delay information, aging delay information and interconnection information, the depth first search algorithm of greedy algorithm is adopted to complete the searching work of the critical circuit path, which verifies that in the circuit life cycle, the key path of the circuit is searched. The key pathways change as a result of the degradation effect. In order to solve the problem of low searching efficiency and slow speed of depth first search algorithm in large-scale circuit test path selection, this paper uses ant colony algorithm to improve the search efficiency of critical path under the condition that the accuracy of path search is guaranteed as much as possible. The experimental results show that both of the two algorithms can search the critical path for the delay test of combinational circuits under the degradation effect, and the ant colony optimization algorithm improves the efficiency of the key path search considering the degradation effect to a certain extent.
【學位授予單位】：哈爾濱工業(yè)大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN407
本文編號：2316879
[Abstract]:Testing plays an important role in the design, production and manufacture of integrated circuits. For combinational logic circuits, it is necessary to test the time delay in each path to determine whether the circuit meets the timing requirements. However, with the increasing of circuit scale, the number of paths in the circuit increases rapidly, so it is difficult to test the delay of all the paths, so it is necessary to select the key path with the largest delay in all the circuit paths. The timing state of the circuit is evaluated by detecting the delay of the critical path. However, with the decreasing of the feature size and the increasing complexity of the circuit structure, the degradation effect is becoming more and more important. The degradation effect has an effect on the delay of each gate element in the circuit, thus affecting the delay on each path in the circuit, which leads to the existence of different critical paths at different times in the circuit life cycle. Therefore, this paper focuses on analyzing the effect of degradation effect on the timing of combinational circuits. According to the variation of circuit delay, we adaptively select the appropriate key path to test the time delay. In order to improve the accuracy of critical path selection and the effectiveness of delay testing. In this paper, the degradation behavior of combinational circuits is combined with the delay test path to solve the problem of searching the delay test path under the influence of degradation effect. Based on the analysis of the degradation behavior of the basic gate cells in the combinational circuits, the relationship between the degradation and the delay changes in the gate cells is studied, and the relationship between the delay changes and the degradation effects of the gate cells in the circuit is established based on the study of the mechanism of the typical degradation effect. On this basis, the topology idea is used to model the circuit structure, to obtain the interconnection of each device unit in the circuit, and then to establish the mathematical model of the test path selection problem of the combinational circuit. On the basis of the acquired delay information, aging delay information and interconnection information, the depth first search algorithm of greedy algorithm is adopted to complete the searching work of the critical circuit path, which verifies that in the circuit life cycle, the key path of the circuit is searched. The key pathways change as a result of the degradation effect. In order to solve the problem of low searching efficiency and slow speed of depth first search algorithm in large-scale circuit test path selection, this paper uses ant colony algorithm to improve the search efficiency of critical path under the condition that the accuracy of path search is guaranteed as much as possible. The experimental results show that both of the two algorithms can search the critical path for the delay test of combinational circuits under the degradation effect, and the ant colony optimization algorithm improves the efficiency of the key path search considering the degradation effect to a certain extent.
【學位授予單位】：哈爾濱工業(yè)大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN407
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，本文編號：2316879
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