【摘要】：大功率復(fù)雜電力電子裝置通常需要半實(shí)物仿真系統(tǒng)來(lái)加速裝置開(kāi)發(fā)和功能驗(yàn)證。然而,商業(yè)化電力電子半實(shí)物仿真系統(tǒng)均由國(guó)外公司壟斷,價(jià)格昂貴,系統(tǒng)升級(jí)維護(hù)費(fèi)用高,開(kāi)放性差,仿真容量和接口數(shù)量也受限;國(guó)內(nèi)針對(duì)電力電子半實(shí)物仿真系統(tǒng)的開(kāi)發(fā)也較少。為此,本文對(duì)適用于電力電子領(lǐng)域的半實(shí)物仿真系統(tǒng)展開(kāi)了研究。解析了半實(shí)物仿真系統(tǒng)的工作原理,本文對(duì)當(dāng)前常見(jiàn)半實(shí)物仿真系統(tǒng)的架構(gòu)及性能進(jìn)行了對(duì)比和分析。綜合其優(yōu)點(diǎn),本文給出了一種基于多FPGA的電力電子半實(shí)物仿真系統(tǒng)架構(gòu)。將半實(shí)物仿真系統(tǒng)的各功能模塊獨(dú)立開(kāi)來(lái),形成不同功能板卡,方便系統(tǒng)擴(kuò)容;采用全硬件FPGA架構(gòu),以多片F(xiàn)PGA作為并行核心運(yùn)算單元,有效增加了系統(tǒng)仿真容量,縮短了仿真步長(zhǎng),保障了系統(tǒng)的仿真精度。針對(duì)本文半實(shí)物仿真系統(tǒng),分析了該架構(gòu)設(shè)計(jì)時(shí)的關(guān)鍵技術(shù)問(wèn)題。首先分析了電力電子實(shí)時(shí)仿真對(duì)計(jì)算資源的要求,其次對(duì)多FPGA的級(jí)聯(lián)拓?fù)溥M(jìn)行了對(duì)比選取,定義了各板卡間的通信結(jié)構(gòu)并對(duì)各功能板卡間數(shù)據(jù)實(shí)時(shí)傳輸需求進(jìn)行了分析,并設(shè)計(jì)了一種滿足以上通信需求的增強(qiáng)型SPI通信方式,實(shí)現(xiàn)了接口板卡與FPGA核心計(jì)算板卡間的數(shù)據(jù)通信;采用LVDS高速通信實(shí)現(xiàn)擴(kuò)容FPGA核心計(jì)算板卡間的數(shù)據(jù)交換。基于以上分析,本文搭建了基于多FPGA的電力電子半實(shí)物仿真平臺(tái),給出了平臺(tái)的具體設(shè)計(jì)過(guò)程,并從仿真容量及精度上對(duì)其性能進(jìn)行了估算與分析。最后采用硬件描述語(yǔ)言搭建了10kV 12級(jí)聯(lián)H橋STATCOM電路模型,載入FPGA核心計(jì)算板卡中,將外部控制器與半實(shí)物仿真平臺(tái)相連接,實(shí)現(xiàn)了10kV STATCOM的硬件在回路閉環(huán)仿真控制。同時(shí)搭建了5級(jí)聯(lián)小功率H橋STATCOM平臺(tái)對(duì)半實(shí)物仿真系統(tǒng)進(jìn)行了更深一步的對(duì)比測(cè)試。實(shí)驗(yàn)結(jié)果表明:仿真步長(zhǎng)2us時(shí),半實(shí)物仿真與Matlab仿真誤差0.5%以內(nèi);系統(tǒng)可以長(zhǎng)時(shí)間穩(wěn)定的對(duì)理想狀況和非理想狀況工作的電力電子裝置進(jìn)行半實(shí)物仿真,通過(guò)半實(shí)物仿真驗(yàn)證的控制器可以直接應(yīng)用于實(shí)際平臺(tái)。
[Abstract]:High power complex power electronic devices usually need hardware-in-the-loop simulation system to accelerate device development and function verification. However, the commercial power electronic hardware-in-the-loop simulation systems are monopolized by foreign companies, the price is high, the cost of system upgrade and maintenance is high, the openness is poor, the simulation capacity and the number of interfaces are also limited. The domestic development of power electronic hardware-in-the-loop simulation system is also less. Therefore, the hardware-in-the-loop simulation system suitable for power electronics is studied in this paper. The working principle of the hardware-in-the-loop simulation system is analyzed and the structure and performance of the current hardware-in-the-loop simulation system are compared and analyzed in this paper. Combining its advantages, this paper presents a power electronics hardware-in-the-loop simulation system architecture based on multiple FPGA. The functional modules of the hardware-in-the-loop simulation system are separated to form different functional boards to facilitate the expansion of the system. With the full hardware FPGA architecture and multi-chip FPGA as the parallel core operation unit, the system simulation capacity is increased effectively, the simulation step is shortened, and the simulation accuracy is guaranteed. The key technical problems in the design of this architecture are analyzed for the hardware-in-the-loop simulation system in this paper. Firstly, the requirements of power electronic real-time simulation for computing resources are analyzed. Secondly, the cascade topology of multiple FPGA is compared and selected, and the communication structure among boards is defined, and the requirement of real-time data transmission between functional boards is analyzed. An enhanced SPI communication mode is designed to meet the above communication requirements, and the data communication between the interface board and the FPGA core computing board is realized. LVDS high-speed communication is used to realize the data exchange between the core computing boards of expanded FPGA. Based on the above analysis, the power electronics hardware-in-the-loop simulation platform based on multi-FPGA is built, the design process of the platform is given, and its performance is estimated and analyzed in terms of simulation capacity and accuracy. Finally, the STATCOM circuit model of 10kV 12 cascaded H bridge is built by using hardware description language, which is loaded into the core computing board of FPGA. The external controller is connected with the hardware-in-the-loop simulation platform, and the hardware in loop closed-loop simulation control of 10kV STATCOM is realized. At the same time, a 5 cascade low power H bridge STATCOM platform is built to further test the hardware-in-the-loop simulation system. The experimental results show that the error between hardware-in-the-loop simulation and Matlab simulation is less than 0.5% when the simulation step is 2us. The system can be used to simulate the power electronic devices working in ideal and non-ideal conditions for a long time and the controller can be directly applied to the real platform through the hardware-in-the-loop simulation.
【學(xué)位授予單位】：南京航空航天大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2016
【分類(lèi)號(hào)】：TN791;TP391.9

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本文編號(hào)：2314659