12位帶數(shù)字校準(zhǔn)的SAR ADC設(shè)計與實(shí)現(xiàn)
發(fā)布時間：2018-11-06 07:30
【摘要】：在納米工藝節(jié)點(diǎn)下,為了滿足系統(tǒng)要求驅(qū)動模數(shù)轉(zhuǎn)換器(ADC)向高速、高精度和低功耗領(lǐng)域發(fā)展。由于SAR ADC具有低功耗、結(jié)構(gòu)簡單、易集成等優(yōu)點(diǎn)成為研究的熱點(diǎn)。為滿足高精度應(yīng)用需求,本文主要研究了在12位SAR ADC中數(shù)字校準(zhǔn)算法,為減小采樣電容的面積開銷及輸入負(fù)載本文采用分裂電容陣列的電容DAC。影響SAR ADC線性度的主要是電容失配,針對這個問題本論文在自校準(zhǔn)算法的基礎(chǔ)上提出了改進(jìn)算法。改進(jìn)算法節(jié)省了1/4的電容開銷,可以直接利用數(shù)字電路對誤差電壓進(jìn)行校準(zhǔn),取得了較好的校準(zhǔn)效果。針對低功耗的要求,在對比分析了4種開關(guān)方式后,選擇能效最好的單片開關(guān)方式,相對于傳統(tǒng)的開關(guān)方式這種方法可以節(jié)省81%的功耗開銷。另外,論文詳細(xì)分析了分裂電容結(jié)構(gòu)原理,為改善線性度,本文設(shè)計了衰減電容為整數(shù)電容的兩段式電容陣列。最后論文通過MATLAB建模的方式確定了關(guān)鍵電路模塊的指標(biāo),本文詳細(xì)分析關(guān)鍵電路模塊原理。最后基于分裂電容陣列的數(shù)字校準(zhǔn)算法設(shè)計實(shí)現(xiàn)了一個12位采樣速率為500KSPs的帶數(shù)字校準(zhǔn)的SAR ADC。版圖后仿結(jié)果表明該ADC獲得輸入頻率為奈奎斯特頻率有效精度11.2位,功耗為1mW,FoM值為5.6pJ/conv-step,在相似的工作條件下Analog Devices公司AD7892系列產(chǎn)品功耗為60mW。
[Abstract]:In order to meet the requirements of the system, (ADC) drives the development of high speed, high precision and low power consumption in nanotechnology nodes. Because of its advantages of low power consumption, simple structure and easy integration, SAR ADC has become a research hotspot. In order to meet the demand of high precision application, this paper mainly studies the digital calibration algorithm in 12-bit SAR ADC. In order to reduce the area overhead of sampling capacitance and input load, this paper adopts the capacitor DAC. of split capacitor array. The linear degree of SAR ADC is mainly affected by capacitor mismatch. In this paper, an improved algorithm based on self-calibration algorithm is proposed. The improved algorithm saves a quarter of the capacitor overhead and can be calibrated directly by using digital circuits to calibrate error voltages, and good calibration results are obtained. According to the requirement of low power consumption, after comparing and analyzing the four switching modes, the single chip switch with the best energy efficiency can save 81% of power consumption compared with the traditional switching method. In addition, the structure principle of split capacitor is analyzed in detail. In order to improve the linearity, a two-segment capacitor array is designed, in which the attenuation capacitance is an integer capacitance. Finally, the key circuit module is determined by MATLAB modeling method, and the principle of the key circuit module is analyzed in detail. Finally, a digital calibration algorithm based on split capacitor array is designed to implement a 12-bit SAR ADC. with digital calibration with 500KSPs sampling rate. The simulation results after layout show that the input frequency of the ADC is 11.2-bit effective precision of Nyquist frequency, the power consumption is 5.6pJ / conv-step. the power consumption of Analog Devices's AD7892 series products is 60mW under similar working conditions.
【學(xué)位授予單位】：國防科學(xué)技術(shù)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN792
本文編號：2313567
[Abstract]:In order to meet the requirements of the system, (ADC) drives the development of high speed, high precision and low power consumption in nanotechnology nodes. Because of its advantages of low power consumption, simple structure and easy integration, SAR ADC has become a research hotspot. In order to meet the demand of high precision application, this paper mainly studies the digital calibration algorithm in 12-bit SAR ADC. In order to reduce the area overhead of sampling capacitance and input load, this paper adopts the capacitor DAC. of split capacitor array. The linear degree of SAR ADC is mainly affected by capacitor mismatch. In this paper, an improved algorithm based on self-calibration algorithm is proposed. The improved algorithm saves a quarter of the capacitor overhead and can be calibrated directly by using digital circuits to calibrate error voltages, and good calibration results are obtained. According to the requirement of low power consumption, after comparing and analyzing the four switching modes, the single chip switch with the best energy efficiency can save 81% of power consumption compared with the traditional switching method. In addition, the structure principle of split capacitor is analyzed in detail. In order to improve the linearity, a two-segment capacitor array is designed, in which the attenuation capacitance is an integer capacitance. Finally, the key circuit module is determined by MATLAB modeling method, and the principle of the key circuit module is analyzed in detail. Finally, a digital calibration algorithm based on split capacitor array is designed to implement a 12-bit SAR ADC. with digital calibration with 500KSPs sampling rate. The simulation results after layout show that the input frequency of the ADC is 11.2-bit effective precision of Nyquist frequency, the power consumption is 5.6pJ / conv-step. the power consumption of Analog Devices's AD7892 series products is 60mW under similar working conditions.
【學(xué)位授予單位】：國防科學(xué)技術(shù)大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN792
【參考文獻(xiàn)】
相關(guān)期刊論文 前2條
1 佟星元;;模/數(shù)轉(zhuǎn)換器結(jié)構(gòu)設(shè)計綜述[J];西安郵電大學(xué)學(xué)報;2013年02期
2 周文婷;李章全;;SAR A/D轉(zhuǎn)換器中電容失配問題的分析[J];微電子學(xué);2007年02期
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