【摘要】：數(shù)模轉(zhuǎn)換器(Digital-to-Analog Converter,簡稱DAC)是數(shù)字電路和模擬電路的重要接口。隨著數(shù)字技術(shù)的快速提升,處理數(shù)字信號的速度越來越快,這就迫切的要求數(shù)模轉(zhuǎn)換器高速高精度。 本文通過研究DAC的基本原理和基本結(jié)構(gòu),并分析每種結(jié)構(gòu)的優(yōu)缺點,然后按照由上到下全定制的方法設(shè)計了一個12位200MHz電流舵型數(shù)模轉(zhuǎn)換器。本文所設(shè)計的DAC主要包括寄存器、譯碼電路、限幅電路、電流源及開關(guān)陣列、偏置電路。本文重點介紹了偏置電路中的帶隙基準電路、電壓-電流轉(zhuǎn)換電路和運算放大器的設(shè)計原理及方法,仿真分析了帶隙基準電路的溫漂系數(shù)和電源抑制比和運算放大器的增益、相位裕度和帶寬。本論文還分析了電流源失配對DAC的SFDR的影響并確定了電流源尺寸,并設(shè)計了一個開關(guān)控制信號的限幅電路,分析了降低時鐘饋通的原理。本文還著重分析了高六位所對應電流源陣列的版圖布局,設(shè)計了譯碼電路中行列溫度計譯碼的選通電路,并對數(shù)字電路中寄存器、鎖存器進行了仿真分析。 本文基于SMIC0.18μm工藝,利用Cadence Specter仿真工具設(shè)計了一個電源電壓為3.3V,滿偏電流為20mA,二進制碼和溫度計碼分段譯碼方式的]2位200MHz電流舵型數(shù)模轉(zhuǎn)換器(DAC)。在此電路中設(shè)計了高頻下具有高輸出阻抗的PMOS共源共柵電流源,從而保證了電路具有良好的SFDR。高位電流源版圖采用了O2Random Walk布局方式來盡量減少因版圖布局引起的誤差。在信號頻率0.999876MHz,采樣頻率200MHz情況下SFDR仿真結(jié)果超過77dB。
[Abstract]:Digital to analog converter (Digital-to-Analog Converter,) is an important interface between digital circuit and analog circuit. With the rapid development of digital technology, the speed of digital signal processing is getting faster and faster. In this paper, the basic principle and structure of DAC are studied, and the advantages and disadvantages of each structure are analyzed. Then a 12-bit 200MHz current-rudder digital-to-analog converter is designed according to the method of top-down customization. The DAC designed in this paper mainly includes register, decoding circuit, limiting circuit, current source and switch array, bias circuit. This paper mainly introduces the design principle and method of bandgap reference circuit, voltage-current conversion circuit and operational amplifier in bias circuit. The temperature drift coefficient, power rejection ratio and gain of operational amplifier of bandgap reference circuit are simulated and analyzed. Phase margin and bandwidth. In this paper, the effect of current source mismatch on SFDR of DAC is analyzed and the size of current source is determined. A limiting circuit of switch control signal is designed, and the principle of reducing clock feedthrough is analyzed. In this paper, the layout of the current source array is analyzed, and the on-off circuit of the column thermometer decoding in the decoding circuit is designed, and the register and latch in the digital circuit are simulated and analyzed. Based on SMIC0.18 渭 m technology and Cadence Specter simulation tool, a 2-bit 200MHz current-rudder digital-to-analog converter (DAC).) with 3.3V power supply voltage, 20mA full bias current, binary code and thermometer code is designed in this paper. In this circuit, a high frequency PMOS source with high output impedance is designed, which ensures that the circuit has a good SFDR.. The high current source layout adopts O2Random Walk layout to minimize the error caused by layout. When the signal frequency is 0.999876MHz and the sampling frequency is 200MHz, the simulation result of SFDR exceeds 77dB.
【學位授予單位】：北方工業(yè)大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN792

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本文編號：2307203