5V工藝下SCR結構在ESD應力下的特性研究及優(yōu)化
發(fā)布時間：2018-10-26 10:52
【摘要】：隨著集成電路制造工藝的發(fā)展,芯片的尺寸越來越小,在帶來芯片速度以及性能方面快速提升的同時,其更容易被靜電釋放(ElectroStatic discharge,簡稱ESD)脈沖損毀。目前,半導體工業(yè)界大約有高達30%的芯片失效是由ESD造成,每年由ESD所造成的損失高達數十億美元。ESD可能對芯片造成兩種問題,一種是直接損毀導致芯片功能喪失,這種損毀在生產時能夠被檢測出來。二是對芯片內部電路產生非致命性損毀,這種損毀在生產時無法檢測,而隨著用戶使用時間的增加,芯片性能變得不穩(wěn)定,引起壽命降低,影響公司信譽。因此,設計出合格的ESD保護結構是提高成品率,樹立公司信譽的關鍵。本文則針對5 V工藝下的IC進行ESD保護研究,并重點研究SCR(Silicon Controlled Rectifier,可控硅整流器)用于5V IC的ESD保護時所存在的問題并優(yōu)化SCR結構。本文先簡單介紹ESD防護理論與常用的ESD保護器件,如:二極管,BJT,GGNMOS,SCR。通過TLP(Transmission Line Pulse,傳輸線脈沖)測試曲線比較SCR與傳統(tǒng)ESD結構的優(yōu)勢與劣勢并建立SCR在被ESD脈沖觸發(fā)到折回(Snapback)時的物理模型,然后介紹5 V器件的ESD設計窗口以及SCR結構直接用于5V芯片所存在的問題,如:觸發(fā)電壓過高,閂鎖效應(Latch up),誤觸發(fā)等。并通過器件仿真獲得I-V特性曲線。在提出多種抗閂鎖SCR的同時,給出一種新型SCR結構,該結構不但能夠用于泄放I/O口的ESD,同時能在保證VDD到GND的ESD路徑不存在閂鎖風險的同時泄放ESD電流。文章的最后,對先進的ESD技術進行了介紹,介紹了主動觸發(fā)電路的概念,并提出一種可抗閂鎖效應的SCR觸發(fā)電路,利用電路仿真軟件spectre對其進行了仿真驗證,分析。最后,在低壓射頻(RF)ESD保護領域,通過RFLDMOS項目介紹了低壓射頻ESD的技術要求,根據TLP測試結果提出了器件優(yōu)化方案。
[Abstract]:With the development of integrated circuit manufacturing technology, the size of chip becomes smaller and smaller, which brings about the rapid improvement of chip speed and performance, and it is more easily damaged by electrostatic release of (ElectroStatic discharge, (ESD) pulse at the same time. At present, about 30% of the chip failures in the semiconductor industry are caused by ESD, which results in billions of dollars of losses caused by ESD every year. ESD may cause two kinds of problems on chips, one is that direct damage results in loss of function of chips. The damage can be detected during production. The other is the non-fatal damage to the internal circuit of the chip, which can not be detected in production. However, with the increase of the user's time, the performance of the chip becomes unstable, which leads to the decrease of the life span and affects the reputation of the company. Therefore, the design of qualified ESD protection structure is the key to improve the product rate and establish the company's reputation. In this paper, the ESD protection of IC in 5V process is studied, and the problems of SCR (Silicon Controlled Rectifier, thyristor rectifier used in ESD protection of 5V IC are studied and the SCR structure is optimized. In this paper, the theory of ESD protection and common ESD protection devices, such as diode, BJT,GGNMOS,SCR., are briefly introduced. The advantage and disadvantage of SCR and traditional ESD structure are compared by TLP (Transmission Line Pulse, transmission line pulse) test curve, and the physical model of SCR is established when it is triggered by ESD pulse to return to (Snapback). Then the paper introduces the ESD design window of 5V device and the problems existing in the SCR structure directly used in 5V chip, such as high trigger voltage, latch effect (Latch up), mistrigger and so on. The I-V characteristic curve is obtained by device simulation. At the same time, a new type of SCR structure is proposed, which can not only be used to release the ESD, of I / O port, but also can discharge ESD current without latch risk in the ESD path from VDD to GND. At the end of the paper, the advanced ESD technology is introduced, the concept of active trigger circuit is introduced, and a SCR trigger circuit which can resist latch effect is proposed. The circuit simulation software spectre is used to verify and analyze it. Finally, in the field of low-voltage RF (RF) ESD protection, the technical requirements of low-voltage RF ESD are introduced through the RFLDMOS project, and the device optimization scheme is proposed according to the test results of TLP.
【學位授予單位】：電子科技大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN405
本文編號：2295480
[Abstract]:With the development of integrated circuit manufacturing technology, the size of chip becomes smaller and smaller, which brings about the rapid improvement of chip speed and performance, and it is more easily damaged by electrostatic release of (ElectroStatic discharge, (ESD) pulse at the same time. At present, about 30% of the chip failures in the semiconductor industry are caused by ESD, which results in billions of dollars of losses caused by ESD every year. ESD may cause two kinds of problems on chips, one is that direct damage results in loss of function of chips. The damage can be detected during production. The other is the non-fatal damage to the internal circuit of the chip, which can not be detected in production. However, with the increase of the user's time, the performance of the chip becomes unstable, which leads to the decrease of the life span and affects the reputation of the company. Therefore, the design of qualified ESD protection structure is the key to improve the product rate and establish the company's reputation. In this paper, the ESD protection of IC in 5V process is studied, and the problems of SCR (Silicon Controlled Rectifier, thyristor rectifier used in ESD protection of 5V IC are studied and the SCR structure is optimized. In this paper, the theory of ESD protection and common ESD protection devices, such as diode, BJT,GGNMOS,SCR., are briefly introduced. The advantage and disadvantage of SCR and traditional ESD structure are compared by TLP (Transmission Line Pulse, transmission line pulse) test curve, and the physical model of SCR is established when it is triggered by ESD pulse to return to (Snapback). Then the paper introduces the ESD design window of 5V device and the problems existing in the SCR structure directly used in 5V chip, such as high trigger voltage, latch effect (Latch up), mistrigger and so on. The I-V characteristic curve is obtained by device simulation. At the same time, a new type of SCR structure is proposed, which can not only be used to release the ESD, of I / O port, but also can discharge ESD current without latch risk in the ESD path from VDD to GND. At the end of the paper, the advanced ESD technology is introduced, the concept of active trigger circuit is introduced, and a SCR trigger circuit which can resist latch effect is proposed. The circuit simulation software spectre is used to verify and analyze it. Finally, in the field of low-voltage RF (RF) ESD protection, the technical requirements of low-voltage RF ESD are introduced through the RFLDMOS project, and the device optimization scheme is proposed according to the test results of TLP.
【學位授予單位】：電子科技大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN405
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