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集成功率NMOSFET的鋰電池保護(hù)芯片關(guān)鍵技術(shù)研究

發(fā)布時(shí)間:2018-10-17 15:03
【摘要】:本文針對(duì)于傳統(tǒng)鋰電池保護(hù)芯片中重要技術(shù)模塊,進(jìn)行了深層次的研究與優(yōu)化,基于tsmc0.18um工藝設(shè)計(jì)了其中相關(guān)改進(jìn)的核心模塊。本著以超低功耗的理念,進(jìn)行了整體芯片電路的設(shè)計(jì)和實(shí)現(xiàn)。對(duì)于過充電保護(hù)、過充電保護(hù)釋放、過放電保護(hù)及過放電保護(hù)釋放功能,只用單個(gè)單管比較器實(shí)現(xiàn)四個(gè)電壓閾值保護(hù)的低功耗模塊,采用遲滯比較器的特性來完成一組雙閾值的比較器輸出翻轉(zhuǎn),再通過電源電壓高低來控制采樣電壓來區(qū)分另外一組的雙閾值,從而完成單個(gè)比較器的四閾值翻轉(zhuǎn)特性,利用帶隙基準(zhǔn)原理將比較器閾值進(jìn)行零溫度處理并進(jìn)行電阻修調(diào),修調(diào)后溫漂最高值為29.08ppm,以保證閾值的精確度。為進(jìn)一步優(yōu)化功耗的損耗,在電路中加入兩相非交疊時(shí)鐘,兩種相位的時(shí)鐘通過控制兩個(gè)比較器的核心結(jié)構(gòu)的斷開與連接工作,使電流和電壓比較器不同時(shí)工作在同一個(gè)相位,從而使得兩組比較器的整體平均功耗降至5uA以內(nèi)。兩相不交疊時(shí)鐘的源時(shí)鐘通過振蕩器來提供,振蕩器的設(shè)計(jì)是基于三級(jí)環(huán)振結(jié)構(gòu)設(shè)計(jì)的環(huán)形振蕩器產(chǎn)生5.46MHZ左右時(shí)鐘頻率,為電路提供了穩(wěn)定的時(shí)鐘脈沖。所設(shè)計(jì)的振蕩器電路不僅為兩相不交疊時(shí)鐘提供輸入,另外其還為延時(shí)模塊提供輸入時(shí)鐘。延時(shí)電路的設(shè)計(jì)思想基本是通過多個(gè)邊沿的D觸發(fā)器完成的,其對(duì)于各個(gè)比較器的輸出信號(hào)進(jìn)行不同的延時(shí),其目的在于防止由電源的噪聲引起比較器意外翻轉(zhuǎn),從而導(dǎo)致的相關(guān)保護(hù)電路誤操作。通過延時(shí)之后,便可消除電源中噪聲的影響。另外,作為鋰電池保護(hù)芯片中另外一個(gè)重要的模塊,作為開關(guān)管的功率NMOSFET的導(dǎo)通電阻優(yōu)化方案,同時(shí)為了保證功率管可以導(dǎo)通大電流的特點(diǎn),選取了特殊的華夫餅式功率管版圖結(jié)構(gòu)的設(shè)計(jì)版圖面積958.7μm*409.5μm導(dǎo)通電阻值為22mΩ,對(duì)比來完成功率管的導(dǎo)通電阻的優(yōu)化,進(jìn)而完成版圖面積的優(yōu)化。
[Abstract]:In this paper, the important technical modules in the traditional lithium battery protection chip are studied and optimized deeply, and the core modules are designed based on the tsmc0.18um process. Based on the idea of ultra-low power consumption, the design and implementation of the whole chip circuit are carried out. For over-charge protection, over-charge protection release, over-discharge protection and over-discharge protection release function, only a single single-transistor comparator is used to realize four low-power modules with voltage threshold protection. The hysteresis comparator is used to complete the output flip of a group of comparators with double thresholds, and the sampling voltage is controlled by the power supply voltage to distinguish the double thresholds of another group, thus the four threshold flipping characteristics of a single comparator are completed. By using the bandgap reference principle, the comparator threshold is treated with zero temperature and the resistor is adjusted. The maximum temperature drift of the comparator is 29.08 ppm, so as to ensure the accuracy of the threshold. In order to further optimize the loss of power consumption, a two-phase non-overlapping clock is added to the circuit. The clock with two phases works by controlling the disconnection and connection of the core structure of the two comparators, which makes the current and voltage comparators work in the same phase at the same time. Thus, the overall average power consumption of the two groups of comparators is reduced to less than 5uA. The source clock of the two-phase non-overlapping clock is provided by the oscillator. The oscillator is designed based on the three-stage ring oscillator structure to generate the 5.46MHZ clock frequency, which provides a stable clock pulse for the circuit. The designed oscillator circuit not only provides input for two phase nonoverlapping clock, but also provides input clock for delay module. The design idea of delay circuit is basically completed by multiple edge D flip-flop, which delays the output signals of each comparator differently, and the purpose of the delay circuit is to prevent the comparator from overturning accidentally by the noise of the power supply. As a result of the related protection circuit misoperation. After the delay, the noise in the power supply can be eliminated. In addition, as another important module in the lithium battery protection chip, as the on-resistance optimization scheme of the switching tube power NMOSFET, at the same time, in order to ensure that the power tube can switch on the characteristics of large current, The designed layout area of the special Wafer type power transistor layout structure is 958.7 渭 m, 409.5 渭 m, the on-resistance value is 22m 惟, which is compared to optimize the on-resistance of the power transistor and then to optimize the layout area.
【學(xué)位授予單位】:北方工業(yè)大學(xué)
【學(xué)位級(jí)別】:碩士
【學(xué)位授予年份】:2017
【分類號(hào)】:TN386;TM912

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