高速低功耗觸發(fā)器的設(shè)計(jì)與特性提取
發(fā)布時(shí)間：2018-10-16 19:37
【摘要】：在超大規(guī)模集成電路設(shè)計(jì)中選擇合適的觸發(fā)器結(jié)構(gòu)是非常重要的,尤其是在高速、低功耗微處理器的設(shè)計(jì)中顯得尤為突出。觸發(fā)器的延時(shí)在整個(gè)時(shí)鐘周期中占據(jù)著重要位置,并且在深亞微米工藝中邏輯長(zhǎng)度也更短的情況下,觸發(fā)器的性能對(duì)處理器的時(shí)鐘頻率有著重要的影響。觸發(fā)器和其他單元共同作用于時(shí)鐘的產(chǎn)生和傳播,其功耗占據(jù)全芯片功耗的20%-40%。所以研究高性能低功耗觸發(fā)器對(duì)于超大規(guī)模集成電路有著重要的作用。本課題主要針對(duì)高性能低功耗觸發(fā)器做了詳細(xì)的研究和仿真,主要研究了以下幾個(gè)方面的內(nèi)容。1)高性能低功耗D觸發(fā)器的設(shè)計(jì)與仿真本文中設(shè)計(jì)的觸發(fā)器有兩種,第一種是自適應(yīng)耦合觸發(fā)器(adaptive-coupling flip-flop,ACFF),該觸發(fā)器的特點(diǎn)是功耗比較低,相對(duì)于傳統(tǒng)主從型觸發(fā)器功耗減少了8.43%,相對(duì)于脈沖型觸發(fā)器減少了55.28%;第二種是脈沖型觸發(fā)器(Transmisson Gate Plulsed Latch,TGPL),其優(yōu)勢(shì)是速度快。在后面電路和版圖級(jí)的仿真中得出的數(shù)據(jù)可以看到TGPL的性能相對(duì)于主從型觸發(fā)器提升45%左右。在后端物理設(shè)計(jì)中所查看的時(shí)序都是參考各個(gè)標(biāo)準(zhǔn)單元以及宏模塊的特性視圖(LIB視圖),在完成觸發(fā)器的設(shè)計(jì)與仿真之后對(duì)所設(shè)計(jì)的觸發(fā)器進(jìn)行了特性視圖的抽取,并且對(duì)不同方法進(jìn)行了實(shí)驗(yàn)和比較。2)D觸發(fā)器測(cè)試電路的設(shè)計(jì)與仿真為了證明所設(shè)計(jì)的D觸發(fā)器能正常工作,并且提取的時(shí)序特征是可靠的,在本文中設(shè)計(jì)了對(duì)觸發(fā)器進(jìn)行實(shí)測(cè)的測(cè)試電路,測(cè)試電路主要分為三部分,第一部分是延時(shí)(時(shí)鐘到輸出的延時(shí))測(cè)量模塊;第二部分是功耗測(cè)量模塊;第三部分是建立保持時(shí)間測(cè)量模塊(TDC)。在電路級(jí)仿真中,延時(shí)測(cè)量模塊測(cè)量誤差為7%左右(5ps以?xún)?nèi)),建立保持時(shí)間測(cè)量模塊的精度可以達(dá)到1.25ps,功耗部分的測(cè)量也兼顧了不同翻轉(zhuǎn)率的情況,對(duì)不同的設(shè)計(jì)進(jìn)行了全面的對(duì)比。綜上所述,本課題包括高性能低功耗D觸發(fā)器的設(shè)計(jì)、特性提取以及實(shí)測(cè)模塊,對(duì)觸發(fā)器進(jìn)行全面的分析和測(cè)量,在獲得時(shí)序上的提升以及能量利用率提高的同時(shí),也保證了觸發(fā)器的可靠性。
[Abstract]:It is very important to choose the appropriate trigger structure in the design of VLSI, especially in the design of high speed and low power microprocessor. The delay of flip-flop occupies an important position in the whole clock cycle, and the performance of flip-flop has an important influence on the clock frequency of the processor when the logic length is shorter in the deep sub-micron process. Flip-flop and other units work together to generate and propagate the clock, and its power consumption accounts for 20-40% of the whole chip power. Therefore, the research of high performance and low power flip-flop plays an important role in VLSI. This paper mainly focuses on the research and simulation of high performance and low power flip-flop. It mainly studies the following aspects. 1) the design and simulation of high performance low power D flip-flop have two kinds of flip-flop designed in this paper. The first is adaptive coupled flip-flop (adaptive-coupling flip-flop,ACFF), which is characterized by low power consumption. Compared with the traditional master-slave flip-flop, the power consumption is reduced by 8.43 steps, compared with the pulse flip-flop, the power consumption is reduced by 55.28%, and the second type is the pulse-type flip-flop (Transmisson Gate Plulsed Latch,TGPL), which has the advantage of fast speed. The data obtained from the simulation of circuit and layout level show that the performance of TGPL is about 45% higher than that of master-slave flip-flop. In order to prove that the designed D flip-flop works normally, and the extracted timing features are reliable, the experiment and comparison of different methods are carried out. 2) the design and simulation of the D flip-flop test circuit are carried out in order to prove that the designed D-flip-flop works normally. The third part is the establishment of the retention time measurement module (TDC). In the circuit level simulation, the measurement error of the delay measurement module is about 7% (within 5ps), the accuracy of the building and holding time measurement module can reach 1.25 pss. the measurement of the power consumption part also takes into account the situation of different turnover rate. A comprehensive comparison of the different designs is made. To sum up, this topic includes the design of high performance and low power D flip-flop, the characteristic extraction and the actual measurement module, and the comprehensive analysis and measurement of the flip-flop, which can improve the timing and energy utilization at the same time. It also ensures the reliability of trigger.
【學(xué)位授予單位】：國(guó)防科學(xué)技術(shù)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類(lèi)號(hào)】：TN783
本文編號(hào)：2275423
[Abstract]:It is very important to choose the appropriate trigger structure in the design of VLSI, especially in the design of high speed and low power microprocessor. The delay of flip-flop occupies an important position in the whole clock cycle, and the performance of flip-flop has an important influence on the clock frequency of the processor when the logic length is shorter in the deep sub-micron process. Flip-flop and other units work together to generate and propagate the clock, and its power consumption accounts for 20-40% of the whole chip power. Therefore, the research of high performance and low power flip-flop plays an important role in VLSI. This paper mainly focuses on the research and simulation of high performance and low power flip-flop. It mainly studies the following aspects. 1) the design and simulation of high performance low power D flip-flop have two kinds of flip-flop designed in this paper. The first is adaptive coupled flip-flop (adaptive-coupling flip-flop,ACFF), which is characterized by low power consumption. Compared with the traditional master-slave flip-flop, the power consumption is reduced by 8.43 steps, compared with the pulse flip-flop, the power consumption is reduced by 55.28%, and the second type is the pulse-type flip-flop (Transmisson Gate Plulsed Latch,TGPL), which has the advantage of fast speed. The data obtained from the simulation of circuit and layout level show that the performance of TGPL is about 45% higher than that of master-slave flip-flop. In order to prove that the designed D flip-flop works normally, and the extracted timing features are reliable, the experiment and comparison of different methods are carried out. 2) the design and simulation of the D flip-flop test circuit are carried out in order to prove that the designed D-flip-flop works normally. The third part is the establishment of the retention time measurement module (TDC). In the circuit level simulation, the measurement error of the delay measurement module is about 7% (within 5ps), the accuracy of the building and holding time measurement module can reach 1.25 pss. the measurement of the power consumption part also takes into account the situation of different turnover rate. A comprehensive comparison of the different designs is made. To sum up, this topic includes the design of high performance and low power D flip-flop, the characteristic extraction and the actual measurement module, and the comprehensive analysis and measurement of the flip-flop, which can improve the timing and energy utilization at the same time. It also ensures the reliability of trigger.
【學(xué)位授予單位】：國(guó)防科學(xué)技術(shù)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類(lèi)號(hào)】：TN783
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