【摘要】：Turbo碼作為20世紀(jì)末通信行業(yè)最偉大的技術(shù)成就之一,它的提出在信道編碼領(lǐng)域具有里程碑式的意義。它不僅擁有接近于Shannon限的性能,更為我們研究編碼理論提供了新的思路和手段。Turbo碼以其優(yōu)越的性能得到了廣泛的應(yīng)用,自然也成為人們競(jìng)相研究的焦點(diǎn)。本文以Turbo碼的研究為出發(fā)點(diǎn),立足于Turbo碼的硬件實(shí)現(xiàn),并在Turbo碼的研究基礎(chǔ)上搭建了一個(gè)硬件通信平臺(tái),方便了對(duì)Turbo碼硬件性能的分析。本文首先對(duì)Turbo碼的基本理論進(jìn)行了系統(tǒng)的研究,介紹了Turbo碼編譯碼器的基本結(jié)構(gòu),推導(dǎo)了MAP類(lèi)算法;同時(shí)進(jìn)行了性能仿真,分析了影響Turbo碼性能的因素。然后,利用滑窗算法的設(shè)計(jì)思路完成了Turbo碼編譯碼器的FPGA實(shí)現(xiàn)。最后,為了能夠靈活有效地對(duì)Turbo碼的編譯碼器的硬件性能進(jìn)行分析,提供了一種硬件系統(tǒng)解決方案。通過(guò)使用應(yīng)用廣泛的以太網(wǎng)技術(shù)搭建了編碼器和譯碼器的聯(lián)調(diào)系統(tǒng)。利用WinPcap技術(shù),以以太網(wǎng)接口為橋梁實(shí)現(xiàn)了FPGA開(kāi)發(fā)板和PC機(jī)之間的信息交換和處理,進(jìn)而完成了整個(gè)基于以太網(wǎng)接口的Turbo碼編譯碼系統(tǒng)的硬件實(shí)現(xiàn)。其間本文也對(duì)千兆以太網(wǎng)接口的FPGA實(shí)現(xiàn)進(jìn)行了研究和設(shè)計(jì)。在系統(tǒng)測(cè)試上,給出了每一個(gè)數(shù)據(jù)處理過(guò)程的詳細(xì)設(shè)計(jì)和仿真結(jié)果。為了完善整個(gè)系統(tǒng),不僅考慮了收發(fā)包之間間隔時(shí)間的設(shè)置,而且在長(zhǎng)幀的處理及其拆包、組包的設(shè)計(jì)上進(jìn)行了相應(yīng)的研究。最終完成了整個(gè)Turbo碼硬件系統(tǒng)的設(shè)計(jì)和仿真,并分析和比較了硬件性能和浮點(diǎn)、定點(diǎn)量化處理性能之間的差別,達(dá)到了預(yù)期的設(shè)計(jì)要求。
[Abstract]:As one of the greatest technological achievements in the communication industry at the end of the 20th century, Turbo code has a landmark significance in the field of channel coding. It not only has the performance close to the Shannon limit, but also provides new ideas and means for us to study the coding theory. Turbo codes have been widely used for their superior performance, and naturally have become the focus of research. This paper takes the research of Turbo code as the starting point, based on the hardware realization of Turbo code, and builds a hardware communication platform based on the research of Turbo code, which facilitates the analysis of the hardware performance of Turbo code. In this paper, the basic theory of Turbo codes is systematically studied, the basic structure of Turbo codes and decoders is introduced, and the MAP class algorithm is deduced. At the same time, the performance simulation is carried out, and the factors influencing the performance of Turbo codes are analyzed. Then, the FPGA implementation of Turbo codec is accomplished by using the design idea of sliding window algorithm. Finally, in order to analyze the hardware performance of Turbo codec flexibly and effectively, a hardware system solution is provided. By using the widely used Ethernet technology, the combined modulation system of encoder and decoder is built. Using WinPcap technology, the information exchange and processing between FPGA development board and PC computer are realized by using Ethernet interface as bridge, and then the hardware implementation of the whole Turbo codec and decode system based on Ethernet interface is completed. Meanwhile, the FPGA implementation of Gigabit Ethernet interface is also studied and designed in this paper. In the system test, the detailed design and simulation results of each data processing process are given. In order to perfect the whole system, not only the setting of the interval between transceiver packets is considered, but also the design of long frame processing and packet unpacking is studied. Finally, the design and simulation of the whole hardware system of Turbo code are completed, and the differences among hardware performance, floating-point and fixed-point quantization processing performance are analyzed and compared, and the expected design requirements are achieved.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類(lèi)號(hào)】：TN911.22;TN791

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本文編號(hào)：2265443