槽柵型二維類超結LDMOS研究
發(fā)布時間：2018-09-03 06:02
【摘要】：本文介紹了橫向雙擴散金屬氧化物半導體場效應晶體管(Lateral Double-diffused Metal Oxide Semiconductor Field Effect Transistor,LDMOS)的基本結構,對其耐壓特性、導通特性、優(yōu)點和應用進行了簡要分析。并對業(yè)界用以改善漂移區(qū)的終端技術進行了較為詳細的歸納和總結,重點對降低表面電場(Reduced SURface Field,RESURF)機理、超結技術和槽型結構的引入做了詳細介紹。接下來從結構角度出發(fā),通過對器件的重新設計,研究了三種新型二維類超結LDMOS結構。采用MEDICI(二維器件仿真軟件)對所提出的器件進行仿真研究和參數(shù)優(yōu)化調整,從而在提升器件擊穿電壓的同時降低比導通電阻。槽柵型二維類超結LDMOS:將縱向交替摻雜的P/N柱應用于槽柵型LDMOS中,并將漏極重摻雜N+區(qū)縱向延伸至與N型柱區(qū)相接。器件處于反向耐壓狀態(tài)時,P柱區(qū)和N柱區(qū)分別處于低電位狀態(tài)和高電位狀態(tài),從而使得漂移區(qū)更好耗盡�；诠β拾雽w物理知識和仿真結果,對該結構導通時的I-V特性和關斷狀態(tài)下的耐高壓能力進行了分析。最終得出500V的擊穿電壓,較普通結構得到了32.6%的優(yōu)化,并且比導通電阻降低了62.5%。槽柵型階梯摻雜P柱區(qū)二維類超結LDMOS:在常規(guī)結構的基礎上,從漂移區(qū)摻雜濃度方面進行優(yōu)化,將橫向變摻雜技術引入到P柱區(qū)的設計中,從源端至漏端摻雜濃度逐漸變低。一方面,在兩個結P1/P2和P2/P3的界面處引入了新的電場峰值對漂移區(qū)電場進行優(yōu)化;另一方面,這樣的柱區(qū)摻雜方式對襯底輔助耗盡效應(Substrate Assisted Depletion Effect,SAD)所帶來的電荷不平衡問題起到了有效的緩解作用。最終將擊穿電壓調整至814V,并且得到的比導通電阻為0.19Ω·cm2。槽型二維類超結LDMOS:在常規(guī)結構的基礎上,從漂移區(qū)形狀方面進行優(yōu)化,在漂移區(qū)中引入槽。一方面,引入的槽對漂移區(qū)進行了折疊,使得其實際長度較橫向尺寸大;另一方面,槽內填充的介質介電常數(shù)比較小,耐壓性能較硅高;再者,同等耐壓級別下器件的漂移區(qū)可以做的更短,因而比導通電阻減小。在漂移區(qū)長度35μm時,得到了與階梯摻雜P柱區(qū)結構在50μm漂移區(qū)下的同等耐壓水平。
[Abstract]:In this paper, the basic structure of transverse double diffusion metal oxide semiconductor field effect transistor (Lateral Double-diffused Metal Oxide Semiconductor Field Effect Transistor,LDMOS) is introduced. The characteristics of voltage resistance, conduction, advantages and applications are briefly analyzed. The terminal technology used to improve the drift zone is summarized in detail. The mechanism of reducing surface electric field (Reduced SURface Field,RESURF), the technology of overjunction and the introduction of slot structure are introduced in detail. Then, from the point of view of structure, through the redesign of the device, three new two-dimensional superjunction LDMOS structures are studied. The MEDICI (two-dimensional device simulation software) is used to simulate and adjust the parameters of the proposed devices so as to reduce the specific on-resistance while increasing the breakdown voltage of the devices. Two-dimensional groove-gate superjunction (LDMOS:) is applied to the groove-gate LDMOS with alternating longitudinal P / N columns, and the drain heavily doped N region is extended longitudinally to the N-type column region. When the device is in the reverse voltage state, the P column region and the N column region are in the low potential state and the high potential state respectively, which makes the drift region more depleted. Based on the knowledge of power semiconductor physics and simulation results, the I-V characteristics of the structure and the high pressure resistance under turn-off state are analyzed. Finally, the breakdown voltage of 500V is optimized by 32.6% compared with the common structure, and the on resistance is reduced by 62.5%. Based on the conventional structure of groove-gate step doped P-column LDMOS:, the doping concentration in drift region is optimized. The transverse variable doping technique is introduced into the design of P-column region, and the doping concentration decreases gradually from source end to drain end. On the one hand, a new peak value of electric field is introduced at the interface of two junctions P1/P2 and P2/P3 to optimize the electric field in the drift region, on the other hand, The columnar doping can effectively alleviate the charge imbalance caused by the substrate-assisted depletion effect (Substrate Assisted Depletion Effect,SAD). The breakdown voltage is adjusted to 814V and the specific on-resistance is 0.19 惟 cm2.. Based on the conventional structure, the groove-type two-dimensional superjunction LDMOS: is optimized from the shape of the drift region, and the slot is introduced into the drift region. On the one hand, the introduced slot folds the drift zone, which makes the actual length larger than the transverse size; on the other hand, the dielectric constant is smaller and the voltage resistance is higher than that of silicon. At the same voltage level, the drift region of the device can be shorter, thus reducing the on-resistance. When the length of drift region is 35 渭 m, the same voltage level as that of step doped P column structure in 50 渭 m drift region is obtained.
【學位授予單位】：南京郵電大學
【學位級別】：碩士
【學位授予年份】：2017
【分類號】：TN386
本文編號：2219052
[Abstract]:In this paper, the basic structure of transverse double diffusion metal oxide semiconductor field effect transistor (Lateral Double-diffused Metal Oxide Semiconductor Field Effect Transistor,LDMOS) is introduced. The characteristics of voltage resistance, conduction, advantages and applications are briefly analyzed. The terminal technology used to improve the drift zone is summarized in detail. The mechanism of reducing surface electric field (Reduced SURface Field,RESURF), the technology of overjunction and the introduction of slot structure are introduced in detail. Then, from the point of view of structure, through the redesign of the device, three new two-dimensional superjunction LDMOS structures are studied. The MEDICI (two-dimensional device simulation software) is used to simulate and adjust the parameters of the proposed devices so as to reduce the specific on-resistance while increasing the breakdown voltage of the devices. Two-dimensional groove-gate superjunction (LDMOS:) is applied to the groove-gate LDMOS with alternating longitudinal P / N columns, and the drain heavily doped N region is extended longitudinally to the N-type column region. When the device is in the reverse voltage state, the P column region and the N column region are in the low potential state and the high potential state respectively, which makes the drift region more depleted. Based on the knowledge of power semiconductor physics and simulation results, the I-V characteristics of the structure and the high pressure resistance under turn-off state are analyzed. Finally, the breakdown voltage of 500V is optimized by 32.6% compared with the common structure, and the on resistance is reduced by 62.5%. Based on the conventional structure of groove-gate step doped P-column LDMOS:, the doping concentration in drift region is optimized. The transverse variable doping technique is introduced into the design of P-column region, and the doping concentration decreases gradually from source end to drain end. On the one hand, a new peak value of electric field is introduced at the interface of two junctions P1/P2 and P2/P3 to optimize the electric field in the drift region, on the other hand, The columnar doping can effectively alleviate the charge imbalance caused by the substrate-assisted depletion effect (Substrate Assisted Depletion Effect,SAD). The breakdown voltage is adjusted to 814V and the specific on-resistance is 0.19 惟 cm2.. Based on the conventional structure, the groove-type two-dimensional superjunction LDMOS: is optimized from the shape of the drift region, and the slot is introduced into the drift region. On the one hand, the introduced slot folds the drift zone, which makes the actual length larger than the transverse size; on the other hand, the dielectric constant is smaller and the voltage resistance is higher than that of silicon. At the same voltage level, the drift region of the device can be shorter, thus reducing the on-resistance. When the length of drift region is 35 渭 m, the same voltage level as that of step doped P column structure in 50 渭 m drift region is obtained.
【學位授予單位】：南京郵電大學
【學位級別】：碩士
【學位授予年份】：2017
【分類號】：TN386
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