【摘要】：隨著集成電子技術的飛速發(fā)展,系統(tǒng)芯片(So C,System-on-a-Chip)得到越來越廣泛的應用,其采用了IP核復用技術,具有集成度高、體積小、性能穩(wěn)定,開發(fā)周期短等諸多優(yōu)勢。但是,芯片集成的功能越來越多,結構也越來越復雜,內部IP核的數(shù)量在持續(xù)增長,測試時間急劇增加。針對這些問題,有必要研究有效的測試調度方法,以實現(xiàn)測試時間的優(yōu)化。主要研究內容有:首先,深入研究可測性設計、內建自測試、邊界掃描測試、掃描測試等So C測試相關技術,提出本課題的總體研究方案。主要從測試體系結構和測試調度算法兩方面展開研究與設計。從測試環(huán)和測試訪問機制兩方面對測試體系結構進行設計;對測試調度問題進行劃分,并從減少測試時間的角度,設計IP核并行測試調度算法。其次,完成了測試體系結構的設計。使用Verilog語言對測試環(huán)的組成部分邊界寄存器、旁路寄存器、指令寄存器進行了功能描述與模塊封裝,實現(xiàn)完整測試環(huán)的構建;設計了一種測試總線按位劃分的測試訪問機制。使用Modelsim軟件對設計的結構進行仿真,驗證功能正確性。然后,對比分析測試調度經典算法,提出基于改進蟻群的測試調度算法,并且應用實例,將本文的調度方法與線性規(guī)劃、遺傳算法進行實驗結果比較,表明該算法可以縮短So C的總測試時間。最后,選用ITC’02標準測試電路d695為被測電路,對其進行可測性設計,搭建了實驗平臺。設計了不同TAM帶寬下的實驗,將本文調度方法與其他方法的實際測試時間進行對比,驗證了該方法的優(yōu)越性。
[Abstract]:With the rapid development of integrated electronic technology, So system on-a-Chip (So) is more and more widely used. It adopts IP core reuse technology, which has many advantages, such as high integration, small volume, stable performance, short development period and so on. However, the number of internal IP cores continues to grow and the test time increases dramatically. To solve these problems, it is necessary to study effective test scheduling methods to optimize test time. The main research contents are as follows: firstly, the related technologies of So C test, such as testability design, built-in self-test, boundary scan test and scan test, are studied deeply, and the overall research scheme of this subject is put forward. Research and design mainly from two aspects of test architecture and test scheduling algorithm. The test architecture is designed from two aspects of test loop and test access mechanism, and the test scheduling problem is partitioned, and the parallel test scheduling algorithm based on IP core is designed from the point of reducing test time. Secondly, the design of test architecture is completed. The function description and module encapsulation of the component boundary register, bypass register and instruction register of the test ring are carried out by using Verilog language, and the construction of the complete test ring is realized, and a test access mechanism of the test bus is designed. The Modelsim software is used to simulate the structure of the design to verify the correctness of the function. Then, by comparing and analyzing the classical test scheduling algorithm, a test scheduling algorithm based on improved ant colony is proposed, and the experimental results of this method are compared with that of linear programming and genetic algorithm. It shows that the algorithm can shorten the total test time of So C. Finally, the ITC'02 standard test circuit d695 is selected as the tested circuit, and the testability design is carried out, and the experimental platform is built. Experiments with different TAM bandwidth are designed and compared with the actual test time of other methods, the superiority of this method is verified.
【學位授予單位】：哈爾濱工業(yè)大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN47

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本文編號：2217597