【摘要】：隨著集成電子技術(shù)的飛速發(fā)展,系統(tǒng)芯片(So C,System-on-a-Chip)得到越來(lái)越廣泛的應(yīng)用,其采用了IP核復(fù)用技術(shù),具有集成度高、體積小、性能穩(wěn)定,開(kāi)發(fā)周期短等諸多優(yōu)勢(shì)。但是,芯片集成的功能越來(lái)越多,結(jié)構(gòu)也越來(lái)越復(fù)雜,內(nèi)部IP核的數(shù)量在持續(xù)增長(zhǎng),測(cè)試時(shí)間急劇增加。針對(duì)這些問(wèn)題,有必要研究有效的測(cè)試調(diào)度方法,以實(shí)現(xiàn)測(cè)試時(shí)間的優(yōu)化。主要研究?jī)?nèi)容有:首先,深入研究可測(cè)性設(shè)計(jì)、內(nèi)建自測(cè)試、邊界掃描測(cè)試、掃描測(cè)試等So C測(cè)試相關(guān)技術(shù),提出本課題的總體研究方案。主要從測(cè)試體系結(jié)構(gòu)和測(cè)試調(diào)度算法兩方面展開(kāi)研究與設(shè)計(jì)。從測(cè)試環(huán)和測(cè)試訪問(wèn)機(jī)制兩方面對(duì)測(cè)試體系結(jié)構(gòu)進(jìn)行設(shè)計(jì);對(duì)測(cè)試調(diào)度問(wèn)題進(jìn)行劃分,并從減少測(cè)試時(shí)間的角度,設(shè)計(jì)IP核并行測(cè)試調(diào)度算法。其次,完成了測(cè)試體系結(jié)構(gòu)的設(shè)計(jì)。使用Verilog語(yǔ)言對(duì)測(cè)試環(huán)的組成部分邊界寄存器、旁路寄存器、指令寄存器進(jìn)行了功能描述與模塊封裝,實(shí)現(xiàn)完整測(cè)試環(huán)的構(gòu)建;設(shè)計(jì)了一種測(cè)試總線按位劃分的測(cè)試訪問(wèn)機(jī)制。使用Modelsim軟件對(duì)設(shè)計(jì)的結(jié)構(gòu)進(jìn)行仿真,驗(yàn)證功能正確性。然后,對(duì)比分析測(cè)試調(diào)度經(jīng)典算法,提出基于改進(jìn)蟻群的測(cè)試調(diào)度算法,并且應(yīng)用實(shí)例,將本文的調(diào)度方法與線性規(guī)劃、遺傳算法進(jìn)行實(shí)驗(yàn)結(jié)果比較,表明該算法可以縮短So C的總測(cè)試時(shí)間。最后,選用ITC’02標(biāo)準(zhǔn)測(cè)試電路d695為被測(cè)電路,對(duì)其進(jìn)行可測(cè)性設(shè)計(jì),搭建了實(shí)驗(yàn)平臺(tái)。設(shè)計(jì)了不同TAM帶寬下的實(shí)驗(yàn),將本文調(diào)度方法與其他方法的實(shí)際測(cè)試時(shí)間進(jìn)行對(duì)比,驗(yàn)證了該方法的優(yōu)越性。
[Abstract]:With the rapid development of integrated electronic technology, So system on-a-Chip (So) is more and more widely used. It adopts IP core reuse technology, which has many advantages, such as high integration, small volume, stable performance, short development period and so on. However, the number of internal IP cores continues to grow and the test time increases dramatically. To solve these problems, it is necessary to study effective test scheduling methods to optimize test time. The main research contents are as follows: firstly, the related technologies of So C test, such as testability design, built-in self-test, boundary scan test and scan test, are studied deeply, and the overall research scheme of this subject is put forward. Research and design mainly from two aspects of test architecture and test scheduling algorithm. The test architecture is designed from two aspects of test loop and test access mechanism, and the test scheduling problem is partitioned, and the parallel test scheduling algorithm based on IP core is designed from the point of reducing test time. Secondly, the design of test architecture is completed. The function description and module encapsulation of the component boundary register, bypass register and instruction register of the test ring are carried out by using Verilog language, and the construction of the complete test ring is realized, and a test access mechanism of the test bus is designed. The Modelsim software is used to simulate the structure of the design to verify the correctness of the function. Then, by comparing and analyzing the classical test scheduling algorithm, a test scheduling algorithm based on improved ant colony is proposed, and the experimental results of this method are compared with that of linear programming and genetic algorithm. It shows that the algorithm can shorten the total test time of So C. Finally, the ITC'02 standard test circuit d695 is selected as the tested circuit, and the testability design is carried out, and the experimental platform is built. Experiments with different TAM bandwidth are designed and compared with the actual test time of other methods, the superiority of this method is verified.
【學(xué)位授予單位】：哈爾濱工業(yè)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類(lèi)號(hào)】：TN47

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本文編號(hào)：2217597