GMAC橋協(xié)議轉(zhuǎn)換電路的功能驗(yàn)證及激勵(lì)自動(dòng)生成方法研究
發(fā)布時(shí)間：2018-08-28 10:15
【摘要】：隨著集成電路規(guī)模以及功能復(fù)雜度的快速發(fā)展,人們?cè)絹?lái)越關(guān)注集成電路功能驗(yàn)證的效率和可靠性。本文設(shè)計(jì)完成了FT-X DSP芯片中的GMAC橋部件,并對(duì)其功能進(jìn)行了充分驗(yàn)證。針對(duì)總線接口類(lèi)電路,提出了一種功能規(guī)范建模方法,形成了功能規(guī)范描述語(yǔ)言。基于所構(gòu)建功能規(guī)范模型,提出了測(cè)試激勵(lì)自動(dòng)生成算法,并使用基于System Verilog的UVM驗(yàn)證方法學(xué)進(jìn)行了設(shè)計(jì)實(shí)現(xiàn)。為所設(shè)計(jì)的GMAC橋部件搭建驗(yàn)證平臺(tái),并為其功能規(guī)范建模,從而自動(dòng)生成測(cè)試激勵(lì),實(shí)驗(yàn)結(jié)果證明這種方法可以有效地提高功能驗(yàn)證的時(shí)間效率和功能覆蓋率。本文的主要工作包括有以下五點(diǎn)內(nèi)容:1)完成FT-X DSP芯片內(nèi)部互連結(jié)構(gòu)中GMAC橋的設(shè)計(jì)實(shí)現(xiàn)工作,對(duì)其設(shè)計(jì)方法進(jìn)行總結(jié)。通過(guò)電路設(shè)計(jì)有限自動(dòng)機(jī),分析GMAC橋電路數(shù)據(jù)傳輸過(guò)程的控制開(kāi)銷(xiāo),并對(duì)GMAC橋電路的數(shù)據(jù)傳輸效率進(jìn)行了系統(tǒng)級(jí)環(huán)境下的實(shí)驗(yàn)驗(yàn)證,證明可以高效完成協(xié)議轉(zhuǎn)換及數(shù)據(jù)傳輸;2)針對(duì)總線接口類(lèi)電路的功能特點(diǎn),對(duì)其功能規(guī)范的特點(diǎn)和組成成分進(jìn)行研究。在此基礎(chǔ)上,對(duì)總線接口類(lèi)電路的功能屬性進(jìn)行分類(lèi),并對(duì)其功能特性進(jìn)行抽象整合,進(jìn)而建立基于功能規(guī)范的總線接口類(lèi)電路功能驗(yàn)證方法;3)使用高階邏輯設(shè)計(jì)功能規(guī)范描述語(yǔ)言,設(shè)計(jì)信號(hào)時(shí)序關(guān)系的邏輯化表達(dá)方式,并通過(guò)BNF范式建立描述語(yǔ)言語(yǔ)法規(guī)則,建立總線接口類(lèi)電路功能規(guī)范點(diǎn)的形式化描述。基于形式化表達(dá)的集成電路功能規(guī)范點(diǎn),建立功能規(guī)范模型;4)以功能規(guī)范模型為基礎(chǔ),設(shè)計(jì)有效測(cè)試向量的生成方法,實(shí)現(xiàn)總線接口類(lèi)電路測(cè)試向量的生成。采用功能覆蓋率驅(qū)動(dòng)的方法,結(jié)合模擬退火算法思想,自動(dòng)判斷是否采納測(cè)試向量為激勵(lì),產(chǎn)生高效的測(cè)試激勵(lì)并保證驗(yàn)證過(guò)程的完備性;實(shí)現(xiàn)多個(gè)電路功能點(diǎn)的并行交叉驗(yàn)證,緩解了對(duì)多個(gè)功能點(diǎn)進(jìn)行驗(yàn)證時(shí)的組合爆炸問(wèn)題;使用基于System Verilog的UVM驗(yàn)證方法學(xué),設(shè)計(jì)驗(yàn)證組件,實(shí)現(xiàn)測(cè)試激勵(lì)自動(dòng)生成算法,完成基于功能規(guī)范模型的功能驗(yàn)證系統(tǒng)設(shè)計(jì),并完成驗(yàn)證系統(tǒng)的測(cè)試、調(diào)試工作;5)對(duì)GMAC橋電路進(jìn)行功能規(guī)范建模,并搭建驗(yàn)證平臺(tái),進(jìn)行激勵(lì)自動(dòng)生成的模擬驗(yàn)證。實(shí)驗(yàn)結(jié)果顯示,GMAC橋電路能夠?qū)崿F(xiàn)功能規(guī)范中描述的全部功能點(diǎn)。當(dāng)功能覆蓋率達(dá)到100%時(shí),基于功能規(guī)范模型的測(cè)試激勵(lì)生成方法比傳統(tǒng)的人工激勵(lì)編寫(xiě)方法產(chǎn)生激勵(lì)數(shù)量平均減少21.15%,并且激勵(lì)生成所需時(shí)間大幅縮減。實(shí)驗(yàn)結(jié)果證明基于功能規(guī)范模型的測(cè)試激勵(lì)自動(dòng)生成方法能夠高效完成的總線接口類(lèi)電路的功能驗(yàn)證。
[Abstract]:With the rapid development of IC scale and functional complexity, more and more attention has been paid to the efficiency and reliability of IC functional verification. In this paper, the GMAC bridge part in FT-X DSP chip is designed and its function is fully verified. In this paper, a modeling method of function specification is proposed for bus interface circuits, and a function specification description language is formed. Based on the function specification model, an automatic generation algorithm of test excitation is proposed, and UVM verification methodology based on System Verilog is used to design and implement it. The verification platform is built for the designed GMAC bridge components, and the function specification is modeled to generate test excitation automatically. The experimental results show that this method can effectively improve the time efficiency and function coverage of function verification. The main work of this paper includes the following five points: 1) finish the design and implementation of GMAC bridge in the interconnect structure of FT-X DSP chip, and summarize its design method. Through circuit design finite automata, the control overhead of GMAC bridge circuit data transmission process is analyzed, and the data transmission efficiency of GMAC bridge circuit is verified by experiments in system level. It is proved that protocol conversion and data transmission can be accomplished efficiently. According to the functional characteristics of bus interface circuit, the characteristics and components of its function specification are studied. On this basis, the functional properties of bus interface class circuits are classified, and their functional characteristics are abstractly integrated. Furthermore, the function verification method of bus interface circuit based on function specification is established. The description language of high order logic design function specification is used to design the logical expression method of signal timing relationship, and the syntax rules of description language are established by BNF normal form. The formal description of the function specification points of bus interface circuit is established. Based on the formal representation of IC functional specification points, a functional specification model is established. Based on the functional specification model, an effective test vector generation method is designed to generate test vectors for bus interface circuits. The method of function coverage driven and simulated annealing algorithm is used to automatically judge whether the test vector is adopted as an incentive to generate efficient test incentives and ensure the completeness of the verification process. The parallel cross verification of multiple circuit function points is realized, and the combinatorial explosion problem is alleviated in the verification of multiple function points. Using UVM verification methodology based on System Verilog, the verification component is designed, and the automatic generating algorithm of test excitation is realized. The function verification system based on the function specification model is designed, and the test of the verification system is completed. The debugging work 5) builds the functional specification modeling for the GMAC bridge circuit, and builds the verification platform for the simulation verification of the excitation automatic generation. The experimental results show that the GMAC bridge circuit can realize all the function points described in the function specification. When the function coverage rate reaches 100, the test incentive generation method based on the function specification model reduces the average number of incentives generated by the traditional manual incentive writing method by 21.15, and the time required to generate the excitation is greatly reduced. The experimental results show that the automatic generation of test excitation based on the function specification model can efficiently verify the function of the bus interface class circuit.
【學(xué)位授予單位】：國(guó)防科學(xué)技術(shù)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類(lèi)號(hào)】：TN402
本文編號(hào)：2209092
[Abstract]:With the rapid development of IC scale and functional complexity, more and more attention has been paid to the efficiency and reliability of IC functional verification. In this paper, the GMAC bridge part in FT-X DSP chip is designed and its function is fully verified. In this paper, a modeling method of function specification is proposed for bus interface circuits, and a function specification description language is formed. Based on the function specification model, an automatic generation algorithm of test excitation is proposed, and UVM verification methodology based on System Verilog is used to design and implement it. The verification platform is built for the designed GMAC bridge components, and the function specification is modeled to generate test excitation automatically. The experimental results show that this method can effectively improve the time efficiency and function coverage of function verification. The main work of this paper includes the following five points: 1) finish the design and implementation of GMAC bridge in the interconnect structure of FT-X DSP chip, and summarize its design method. Through circuit design finite automata, the control overhead of GMAC bridge circuit data transmission process is analyzed, and the data transmission efficiency of GMAC bridge circuit is verified by experiments in system level. It is proved that protocol conversion and data transmission can be accomplished efficiently. According to the functional characteristics of bus interface circuit, the characteristics and components of its function specification are studied. On this basis, the functional properties of bus interface class circuits are classified, and their functional characteristics are abstractly integrated. Furthermore, the function verification method of bus interface circuit based on function specification is established. The description language of high order logic design function specification is used to design the logical expression method of signal timing relationship, and the syntax rules of description language are established by BNF normal form. The formal description of the function specification points of bus interface circuit is established. Based on the formal representation of IC functional specification points, a functional specification model is established. Based on the functional specification model, an effective test vector generation method is designed to generate test vectors for bus interface circuits. The method of function coverage driven and simulated annealing algorithm is used to automatically judge whether the test vector is adopted as an incentive to generate efficient test incentives and ensure the completeness of the verification process. The parallel cross verification of multiple circuit function points is realized, and the combinatorial explosion problem is alleviated in the verification of multiple function points. Using UVM verification methodology based on System Verilog, the verification component is designed, and the automatic generating algorithm of test excitation is realized. The function verification system based on the function specification model is designed, and the test of the verification system is completed. The debugging work 5) builds the functional specification modeling for the GMAC bridge circuit, and builds the verification platform for the simulation verification of the excitation automatic generation. The experimental results show that the GMAC bridge circuit can realize all the function points described in the function specification. When the function coverage rate reaches 100, the test incentive generation method based on the function specification model reduces the average number of incentives generated by the traditional manual incentive writing method by 21.15, and the time required to generate the excitation is greatly reduced. The experimental results show that the automatic generation of test excitation based on the function specification model can efficiently verify the function of the bus interface class circuit.
【學(xué)位授予單位】：國(guó)防科學(xué)技術(shù)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類(lèi)號(hào)】：TN402
【參考文獻(xiàn)】
相關(guān)期刊論文 前1條
1 賈建革;段新安;李詠雪;;VLSI超大規(guī)模集成電路測(cè)試和驗(yàn)證的發(fā)展趨勢(shì)[J];中國(guó)測(cè)試技術(shù);2005年06期
相關(guān)碩士學(xué)位論文 前1條
1 楊_";基于斷言的功能驗(yàn)證方法研究[D];東南大學(xué);2006年
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