集成電路靜電保護網(wǎng)絡(luò)及器件特性研究和設(shè)計優(yōu)化
發(fā)布時間：2018-08-24 19:55
【摘要】：隨著微電子技術(shù)的不斷發(fā)展,特征尺寸的降低和新工藝技術(shù)的引入,集成電路和系統(tǒng)對ESD應力越來越敏感。本文在0.35um的工藝下,分析了常見的ESD保護器件的工作特性及仿真結(jié)果,設(shè)計出基本箝位電路網(wǎng)絡(luò)。以中芯國際生產(chǎn)的芯片JSR26C32以及TI公司的CD54HC123F3A測試結(jié)果,分析失效原因并且提出改進措施。主要的研究內(nèi)容如下:論文針對ESD的基本概念進行了分析。對四種的ESD保護器件的工作原理進行了研究與仿真。重點對ggNMOS在ESD脈沖下的電流分布及熱分布進行仿真。對比了SCR和LVTSCR結(jié)構(gòu)的觸發(fā)電壓以及保持電壓。分析了依靠RC和有源器件開啟的箝位網(wǎng)絡(luò)。利用HSPICE仿真分析了不同大小的柵漏耦合電容對HBM和MM應力下箝位電壓的影響,對實際的防護電路設(shè)計參數(shù)的選取提供了理論支持。針對多電源領(lǐng)域的應用,改進了一款箝位電路。該電路具有兩倍箝位電壓、堆疊MOS構(gòu)成的高電壓容限的箝位電路,并且仿真分析得到的箝位電壓為10V驗證了理論;最后分析了兩級ESD保護電路在基于ESD軌和局部箝位兩種防護策略的應用,仿真驗證了一款三端二極管結(jié)構(gòu)構(gòu)成的兩級保護電路的實際防護效果。設(shè)計了針對上海航天技術(shù)研究院提供的JSR26C32以及TI公司的CD54HC123F3A的實驗方法。研究了兩種芯片針對不同的管腳的ESD保護電路原理、尺寸及布局設(shè)計。設(shè)計了針對三種測試模型的測試方案,起始電壓及步長的選擇,并且確定了該芯片的失效閾值ESDV。提出了三種判斷芯片失效的標準。通過光學顯微鏡及其他設(shè)備的幫助,在加電狀態(tài)下找出失效點。繼續(xù)剖片找出失效位置,結(jié)合電路邏輯圖與版圖布局給出失效的分析結(jié)果。參考國內(nèi)外的文獻提出器件及布局的改進措施。綜上所述,本文以常見的ESD保護器件和箝位網(wǎng)絡(luò)的設(shè)計方法,在亞微米尺度分析ESD防護器件ggNMOS和SCR的性能。分析仿真了箝位網(wǎng)絡(luò)及針對高電壓容限的電路設(shè)計。結(jié)合實際芯片的電路原理和布局,分析了兩種芯片的失效原因,為后續(xù)的ESD改進設(shè)計提供了指導。
[Abstract]:With the development of microelectronics, the reduction of feature size and the introduction of new technology, integrated circuits and systems are more and more sensitive to ESD stress. In this paper, the operating characteristics and simulation results of common ESD protection devices are analyzed under the technology of 0.35um, and the basic clamping circuit network is designed. Based on the JSR26C32 chip produced by SMIC and the CD54HC123F3A test results of TI Company, the causes of failure are analyzed and the improvement measures are put forward. The main research contents are as follows: the basic concept of ESD is analyzed in this paper. The working principle of four kinds of ESD protection devices is studied and simulated. The current distribution and heat distribution of ggNMOS under ESD pulse are simulated. The trigger voltage and hold voltage of SCR and LVTSCR are compared. The clamping network which is opened by RC and active device is analyzed. The effects of different sizes of gate leakage coupling capacitors on clamping voltage under HBM and MM stress are analyzed by HSPICE simulation, which provides theoretical support for the selection of design parameters of practical protection circuits. A clamping circuit is improved for the application of multi-power supply field. The circuit has double clamping voltage and high voltage tolerance clamping circuit composed of stacked MOS. The simulation results show that the clamping voltage is 10V. Finally, the application of two-stage ESD protection circuit based on ESD rail and local clamping is analyzed, and the actual protection effect of a three-terminal diode structure is verified by simulation. The experimental methods for JSR26C32 provided by Shanghai Aerospace Technology Research Institute and CD54HC123F3A of TI Company are designed. The principle, size and layout of ESD protection circuit for different pins are studied. The test scheme for three test models, the choice of starting voltage and step size are designed, and the failure threshold ESDV. of the chip is determined. Three criteria for judging chip failure are proposed. Through the help of optical microscope and other equipment to find out the failure point in the power-on state. Continue to slice to find out the failure location, combined with the circuit logic diagram and layout to give the failure analysis results. The improvement measures of device and layout are put forward with reference to the literature at home and abroad. To sum up, the performance of ESD protection devices ggNMOS and SCR is analyzed at submicron scale by the common design methods of ESD protection devices and clamping networks. The clamp network and the circuit design for high voltage tolerance are analyzed and simulated. Combined with the circuit principle and layout of the actual chip, the failure reasons of the two kinds of chips are analyzed, which provides guidance for improving the design of ESD in the future.
【學位授予單位】：西安電子科技大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN402
本文編號：2201862
[Abstract]:With the development of microelectronics, the reduction of feature size and the introduction of new technology, integrated circuits and systems are more and more sensitive to ESD stress. In this paper, the operating characteristics and simulation results of common ESD protection devices are analyzed under the technology of 0.35um, and the basic clamping circuit network is designed. Based on the JSR26C32 chip produced by SMIC and the CD54HC123F3A test results of TI Company, the causes of failure are analyzed and the improvement measures are put forward. The main research contents are as follows: the basic concept of ESD is analyzed in this paper. The working principle of four kinds of ESD protection devices is studied and simulated. The current distribution and heat distribution of ggNMOS under ESD pulse are simulated. The trigger voltage and hold voltage of SCR and LVTSCR are compared. The clamping network which is opened by RC and active device is analyzed. The effects of different sizes of gate leakage coupling capacitors on clamping voltage under HBM and MM stress are analyzed by HSPICE simulation, which provides theoretical support for the selection of design parameters of practical protection circuits. A clamping circuit is improved for the application of multi-power supply field. The circuit has double clamping voltage and high voltage tolerance clamping circuit composed of stacked MOS. The simulation results show that the clamping voltage is 10V. Finally, the application of two-stage ESD protection circuit based on ESD rail and local clamping is analyzed, and the actual protection effect of a three-terminal diode structure is verified by simulation. The experimental methods for JSR26C32 provided by Shanghai Aerospace Technology Research Institute and CD54HC123F3A of TI Company are designed. The principle, size and layout of ESD protection circuit for different pins are studied. The test scheme for three test models, the choice of starting voltage and step size are designed, and the failure threshold ESDV. of the chip is determined. Three criteria for judging chip failure are proposed. Through the help of optical microscope and other equipment to find out the failure point in the power-on state. Continue to slice to find out the failure location, combined with the circuit logic diagram and layout to give the failure analysis results. The improvement measures of device and layout are put forward with reference to the literature at home and abroad. To sum up, the performance of ESD protection devices ggNMOS and SCR is analyzed at submicron scale by the common design methods of ESD protection devices and clamping networks. The clamp network and the circuit design for high voltage tolerance are analyzed and simulated. Combined with the circuit principle and layout of the actual chip, the failure reasons of the two kinds of chips are analyzed, which provides guidance for improving the design of ESD in the future.
【學位授予單位】：西安電子科技大學
【學位級別】：碩士
【學位授予年份】：2015
【分類號】：TN402
【參考文獻】
相關(guān)期刊論文 前1條
1 朱科翰;于宗光;董樹榮;韓雁;;0.18μm混合信號RFCMOS工藝中新型低觸發(fā)電壓雙向SCR靜電防護器件的設(shè)計(英文)[J];半導體學報;2008年11期
，本文編號：2201862
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