發(fā)布時(shí)間：2018-08-10 20:55

【摘要】：目前,隨著SoC (System on Chip)芯片規(guī)模及復(fù)雜度的快速增長(zhǎng),傳統(tǒng)的驗(yàn)證技術(shù)已經(jīng)不能滿足項(xiàng)目進(jìn)度的需求。而且由于IP復(fù)用技術(shù)的廣泛應(yīng)用,工程師往往不得不花費(fèi)大量的時(shí)間去了解IP核設(shè)計(jì)細(xì)節(jié),并為其開(kāi)發(fā)復(fù)雜的驗(yàn)證平臺(tái)和測(cè)試激勵(lì)。面對(duì)巨大的驗(yàn)證壓力,驗(yàn)證業(yè)界開(kāi)發(fā)出了一套新的驗(yàn)證方法學(xué)UVM (Universal Verification Methodology),它有著強(qiáng)大的、已證實(shí)的工業(yè)基礎(chǔ),是未來(lái)驗(yàn)證技術(shù)的發(fā)展趨勢(shì)。本文在詳細(xì)介紹UVM驗(yàn)證方法學(xué)的核心思想和寄存器模型的基礎(chǔ)上,采用UVM驗(yàn)證方法搭建了SSD(Solid State Disk)主控SoC芯片的驗(yàn)證平臺(tái),包括可重用接口UVCs (UVM Verification Component)、模塊和系統(tǒng)UVCs以及系統(tǒng)寄存器模型等。通過(guò)分析芯片的系統(tǒng)架構(gòu)和功能需求,提煉出芯片待驗(yàn)證功能點(diǎn),并利用搭建好的驗(yàn)證平臺(tái)對(duì)芯片進(jìn)行驗(yàn)證,給出了各模塊的驗(yàn)證結(jié)果以及覆蓋率分析。本課題所設(shè)計(jì)的UVM驗(yàn)證平臺(tái)具有高效率、高可重用性的特點(diǎn),其支持受約束激勵(lì)自動(dòng)生成、自動(dòng)檢測(cè)和功能覆蓋率等功能,大大提高了驗(yàn)證的完備性和效率。并且驗(yàn)證平臺(tái)可隨時(shí)按需求定制平臺(tái)架構(gòu)、添加相關(guān)驗(yàn)證組件UVC、修改隨機(jī)向量約束條件等,使其可重用性和靈活性最大化。另外,寄存器模型為驗(yàn)證平臺(tái)提供了一個(gè)方便跟蹤和訪問(wèn)DUT內(nèi)部寄存器的方法,可用于監(jiān)控待驗(yàn)證芯片行為和生成更高抽象層次的激勵(lì)。本文所研究的驗(yàn)證方法高效且實(shí)用,可應(yīng)用于其它SSD主控芯片或類(lèi)似芯片的驗(yàn)證當(dāng)中。
[Abstract]:At present, with the rapid growth of SoC (System on Chip) chip size and complexity, the traditional verification technology can not meet the needs of project schedule. Because of the wide application of IP reuse technology, engineers often have to spend a lot of time to understand the details of IP core design, and develop complex verification platform and test incentives for it. In the face of great verification pressure, the verification industry has developed a new verification methodology, UVM (Universal Verification Methodology), which has a strong and proven industrial foundation, and is the development trend of verification technology in the future. On the basis of introducing the core idea and register model of UVM verification methodology in detail, this paper uses UVM verification method to build the verification platform of SSD (Solid State Disk) master SoC chip. It includes reusable interface UVCs (UVM Verification Component), module and system UVCs, system register model and so on. By analyzing the system architecture and functional requirements of the chip, the functional points of the chip to be verified are extracted, and the verification results and coverage analysis of each module are given by using a good verification platform. The UVM verification platform designed in this paper has the characteristics of high efficiency and high reusability. It supports the functions of automatic generation of constrained excitation, automatic detection and function coverage, which greatly improves the completeness and efficiency of verification. And the verification platform can customize the platform architecture according to the demand at any time, add the related verification component UVC, modify the constraint condition of random vector, etc., make its reusability and flexibility maximized. In addition, the register model provides a convenient way to track and access the internal register of DUT for the verification platform, which can be used to monitor the behavior of the chip to be verified and to generate a higher abstract level of excitation. The verification method studied in this paper is efficient and practical, and can be applied to other SSD master chips or similar chips.
【學(xué)位授予單位】：東南大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類(lèi)號(hào)】：TN47

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本文編號(hào)：2176180