【摘要】：隨著半導(dǎo)體行業(yè)的發(fā)展和電子設(shè)計(jì)自動(dòng)化技術(shù)進(jìn)步,芯片容量按照摩爾定律每18個(gè)月增長(zhǎng)一倍,而應(yīng)用的計(jì)算量卻以幾何指數(shù)增加。限于器件工藝技術(shù),單純通過提高單核芯片主頻,已經(jīng)無法滿足現(xiàn)代應(yīng)用計(jì)算復(fù)雜、數(shù)據(jù)量大、實(shí)時(shí)性要求高的特點(diǎn)。在此背景下,多種新型的系統(tǒng)架構(gòu)應(yīng)運(yùn)而生,新型計(jì)算技術(shù)的發(fā)展也日趨成熟。本文設(shè)計(jì)并優(yōu)化了基于FPGA的多核混合可重構(gòu)計(jì)算系統(tǒng),可穩(wěn)定地運(yùn)行在100MHz時(shí)鐘頻率下。在優(yōu)化前后的系統(tǒng)上完成多種浮點(diǎn)密集型計(jì)算應(yīng)用,既驗(yàn)證了系統(tǒng)計(jì)算的正確性,又證明了優(yōu)化策略的可行性。論文的主要工作如下：1.總結(jié)了可重構(gòu)計(jì)算以及多核技術(shù)的發(fā)展和研究現(xiàn)狀,根據(jù)多核可重構(gòu)計(jì)算系統(tǒng)的設(shè)計(jì)方向設(shè)計(jì)了可重構(gòu)計(jì)算系統(tǒng)模型。2.設(shè)計(jì)并優(yōu)化可重構(gòu)計(jì)算核,主要包括可重構(gòu)計(jì)算陣列和流水線。流水線主要用于執(zhí)行不合適可重構(gòu)計(jì)算處理的離散和控制指令,增加了系統(tǒng)對(duì)算法的適應(yīng)性,提高了系統(tǒng)的計(jì)算效率。同時(shí)針對(duì)兩者的特點(diǎn)提出了多種優(yōu)化策略。3.設(shè)計(jì)了片上網(wǎng)絡(luò)作為多個(gè)計(jì)算核心進(jìn)行并行計(jì)算所需的高效通信架構(gòu),支持多路數(shù)據(jù)并行傳輸；通過優(yōu)化硬件控制邏輯和采用合理的存儲(chǔ)空間設(shè)計(jì)有效減少了數(shù)據(jù)通信時(shí)間,提升了計(jì)算效率。4.通過在優(yōu)化前后的系統(tǒng)上映射浮點(diǎn)矩陣乘法、矩陣求逆、實(shí)對(duì)稱矩陣特征分解以及運(yùn)動(dòng)評(píng)估算法,驗(yàn)證了原型系統(tǒng)的高效性和靈活性,以及優(yōu)化策略的良好效果。
[Abstract]:With the development of semiconductor industry and the advance of electronic design automation technology, the chip capacity has doubled every 18 months according to Moore's law, while the computational complexity of application has increased by geometric exponent. Limited to the device technology, it can not meet the requirements of modern application such as complex calculation, large amount of data and high real-time performance simply by improving the main frequency of single core chip. Under this background, many kinds of new system architecture emerge as the times require, and the development of new computing technology is maturing day by day. This paper designs and optimizes a multi-core hybrid reconfigurable computing system based on FPGA, which can run stably at 100MHz clock frequency. A variety of floating-point intensive computing applications are completed in the system before and after optimization, which not only verifies the correctness of the system calculation, but also proves the feasibility of the optimization strategy. The main work of the thesis is as follows: 1: 1. This paper summarizes the development and research status of reconfigurable computing and multi-kernel technology, and designs a reconfigurable computing system model .2. according to the design direction of multi-core reconfigurable computing system. Reconfigurable computing cores are designed and optimized, including reconfigurable computing arrays and pipelining. Pipelining is mainly used to execute discrete and control instructions which are not suitable for reconfigurable computation processing. It increases the adaptability of the system to the algorithm and improves the efficiency of the system. At the same time, according to the characteristics of the two, we put forward a variety of optimization strategies. An efficient communication architecture for parallel computing is designed, which supports multi-channel parallel data transmission, and reduces the time of data communication by optimizing hardware control logic and adopting reasonable storage space design. Improved computational efficiency. 4. By mapping floating-point matrix multiplication, matrix inversion, real symmetric matrix characteristic decomposition and motion evaluation algorithm on the system before and after optimization, the efficiency and flexibility of the prototype system and the good effect of the optimization strategy are verified.
【學(xué)位授予單位】：合肥工業(yè)大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2015
【分類號(hào)】：TN791

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