【摘要】：碳化硅(Silicon Carbide)半導(dǎo)體材料憑借臨界擊穿電場(chǎng)高、熱導(dǎo)率高、熱載流子飽和漂移速度高、抗輻照能力強(qiáng)等特點(diǎn),已經(jīng)成為國(guó)際功率半導(dǎo)體領(lǐng)域的研究熱點(diǎn)。與Si基功率器件相比,Si C功率半導(dǎo)體器件及模塊不僅功率更大,而且開(kāi)關(guān)損耗和系統(tǒng)體積也降低一半以上。國(guó)內(nèi)在SiC MOSFET功率器件的研究方面才剛剛起步,與國(guó)際水平差距還比較顯著。本文立足于國(guó)內(nèi)科研單位的工藝平臺(tái),設(shè)計(jì)優(yōu)化了擊穿電壓1700V 4H-SiC DMOS晶體管結(jié)構(gòu)參數(shù),繪制了器件版圖,并進(jìn)行了流片實(shí)驗(yàn)驗(yàn)證和測(cè)試分析,為后續(xù)國(guó)內(nèi)1700V SiC DMOS晶體管的應(yīng)用研究提供了理論支持和技術(shù)指導(dǎo)。本論文首先利用半導(dǎo)體二維數(shù)值分析軟件Silvaco的器件模擬模塊Atlas對(duì)擊穿電壓1700V的4H-SiC DMOS元胞結(jié)構(gòu)參數(shù)進(jìn)行設(shè)計(jì),折衷?xún)?yōu)化柵氧化層厚度、JFET寬度、溝道長(zhǎng)度和P_base區(qū)濃度等器件結(jié)構(gòu)參數(shù)對(duì)擊穿電壓、閾值電壓和導(dǎo)通電阻的影響。其次在確定元胞參數(shù)后,考慮到曲率效應(yīng),分別研究了場(chǎng)板終端、單步刻蝕型JTE終端和場(chǎng)限環(huán)終端對(duì)器件擊穿電壓的影響。此外,針對(duì)高電場(chǎng)應(yīng)力下Si C DMOS器件的柵介質(zhì)容易發(fā)生FN隧穿,從而降低器件可靠性的問(wèn)題,研究了一種降低FN隧穿效應(yīng)的基于SiO2和HfO2等高K材料組成的SiC MOS復(fù)合柵結(jié)構(gòu)。接下來(lái)本文對(duì)經(jīng)過(guò)1300℃高溫氧化并在NO氣體中退火的4H-SiC MOS電容界面特性進(jìn)行研究。測(cè)試結(jié)果表明,高溫氧化后NO退火能夠降低SiO2/SiC界面態(tài)密度,而且隨著退火溫度和時(shí)間的提高,界面態(tài)密度會(huì)進(jìn)一步降低。最后基于器件仿真設(shè)計(jì),繪制出1700V 4H-SiC DMOS器件版圖,同時(shí)立足于國(guó)內(nèi)科研院所的工藝平臺(tái),進(jìn)行了流片實(shí)驗(yàn)和測(cè)試結(jié)果分析。實(shí)驗(yàn)流片出來(lái)的4H-Si C DMOS器件擊穿電壓達(dá)到2500V,閾值電壓4.8V,達(dá)到設(shè)計(jì)目標(biāo),為后續(xù)開(kāi)展1700V的SiC DMOS器件產(chǎn)業(yè)化的研究提供了有力支撐。
[Abstract]:Silicon carbide (sic) (Silicon Carbide) semiconductor material has become a research hotspot in the field of power semiconductor because of its high critical breakdown electric field, high thermal conductivity, high saturation drift velocity of hot carriers, strong radiation resistance and so on. Compared with Si-based power devices, Si C power semiconductor devices and modules not only have higher power, but also reduce switching loss and system volume by more than half. The research of SiC MOSFET power devices in China has just started, and the gap with the international level is significant. Based on the technology platform of domestic scientific research units, this paper designs and optimizes the structure parameters of 1700V 4H-SiC DMOS transistor, draws the layout of the device, and carries out the verification and test analysis of the flow sheet experiment. It provides theoretical support and technical guidance for the application research of 1700V SiC DMOS transistors in China. In this paper, the device simulation module Atlas of semiconductor two-dimensional numerical analysis software Silvaco is used to design the cell structure parameters of 4H-SiC DMOS with a breakdown voltage of 1700V, and the thickness of gate oxide is optimized to optimize the width of JFET. The influence of channel length and P_base concentration on breakdown voltage, threshold voltage and on-resistance. Secondly, after determining the cell parameters and considering the curvature effect, the effects of field board terminal, single-step etching JTE terminal and field limiting loop terminal on the breakdown voltage of the device are studied respectively. In addition to the problem that FN tunneling is easy to occur in the gate dielectric of Si C DMOS devices under high electric field stress thus reducing the reliability of FN devices a SiC MOS composite gate structure based on high K materials such as SiO2 and HfO2 is studied to reduce the FN tunneling effect. The interface characteristics of 4H-SiC MOS capacitors after high temperature oxidation at 1300 鈩，

本文編號(hào)：2154337