協(xié)同緩解電路NBTI效應與泄漏功耗技術研究
發(fā)布時間：2018-07-21 22:08
【摘要】：隨著集成電路的工藝水平進入到納米層級時,器件的諸多負面效應逐漸突顯出來,其中負偏置溫度不穩(wěn)定性(Negative Bias Temperature Instability, NBTI)效應成為影響集成電路可靠性與使用壽命的重要因素之一。長期的NBTI效應會造成電路的時延增加,速度降低,并最終導致電路的功能失效。針對NBTI效應的分析與研究已成為集成電路抗老化設計的重要課題之一。同時,電壓的非等比縮小帶來較大的泄漏功耗(Leakage Power),嚴重影響到器件的使用壽命,研究如何降低電路的泄漏功耗也是低功耗設計領域的重要內容之一�，F(xiàn)有方案通過輸入向量控制(IVC)結合門替換(GR)技術緩解負偏置溫度不穩(wěn)定性(NBTI)引起的電路老化,卻存在GR應用可能破壞IVC抗老化效果的問題,本文提出了一種輸入向量控制與傳輸門(TG)插入相結合的方案來緩解電路的NBTI效應,對于切分的子電路動態(tài)回溯尋找其最優(yōu)輸入向量,在不破壞IVC優(yōu)化效果的情況下,通過插入傳輸門來消除合并子電路時產生的邏輯沖突,最終得到復原后的目標電路的最優(yōu)輸入控制向量。實驗結果表明:本文的IVC與傳輸門結合方案對于電路的時延退化改善率為57.74%,面積開銷為1.69%,與IVC與GR方案相比,時延退化改善率提高0.67倍,面積開銷降低0.42倍,體現(xiàn)了本文方案能夠更好的緩解電路的NBTI老化效應。本文的IVC與傳輸門插入方案僅考慮到對于NBTI效應的緩解,卻未能減少電路的靜態(tài)泄漏功耗,為了滿足集成電路設計的低功耗要求,本文給出了協(xié)同緩解電路NBTI與降低泄漏功耗方案,在IVC與傳輸門插入方案基礎上加以操作;當尋找子電路最優(yōu)輸入向量時,在非關鍵路徑上降低電路的泄漏功耗,同時在關鍵路徑上,基于緩解電路NBTI效應的基礎上進一步減少泄漏功耗,最終通過合并子電路得到最優(yōu)輸入向量來協(xié)同緩解電路的NBTI效應與降低泄漏功耗。相比較IVC與GR的協(xié)同優(yōu)化方案,本文方案在電路泄漏功耗幾乎相同的前提下,時延退化改善率提高了 0.51倍,更加有利于NBTI效應的緩解與泄漏功耗的降低。
[Abstract]:As the process level of integrated circuits reaches the nanometer level, many negative effects of the devices gradually become apparent. The negative bias temperature instability (NBTI) effect is one of the most important factors affecting the reliability and service life of integrated circuits. The long term NBTI effect will lead to the increase of delay and the decrease of the speed of the circuit, and ultimately lead to the functional failure of the circuit. The analysis and research of NBTI effect has become one of the most important topics in the design of integrated circuits. At the same time, the reduction of voltage non-equal ratio brings a large leakage power (Leakage Power), which seriously affects the service life of the device. The research on how to reduce the leakage power is also one of the important contents in the field of low-power design. The current scheme uses input vector control (IVC) combined with gate substitution (gr) to mitigate the circuit aging caused by negative bias temperature instability (NBTI), but there is a problem that the application of gr may undermine the anti-aging effect of IVC. In this paper, a scheme combining input vector control and transmission gate (TG) insertion is proposed to mitigate the NBTI effect of the circuit. The optimal input control vector of the restored target circuit is obtained by inserting the transmission gate to eliminate the logic conflict caused by the merging sub-circuit. The experimental results show that the time delay degradation improvement rate of the proposed IVC and transmission gate scheme is 57.74 and the area overhead is 1.69. Compared with the IVC and gr scheme, the delay degradation improvement rate is 0.67 times higher and the area cost is reduced by 0.42 times. This scheme can better alleviate the NBTI aging effect of the circuit. The IVC and transmission gate insertion scheme in this paper only considers the mitigation of NBTI effect, but fails to reduce the static leakage power consumption of the circuit. In order to meet the low power requirement of integrated circuit design, the IVC and the transmission gate insert scheme only consider the mitigation of NBTI effect. In this paper, the cooperative mitigation circuit NBTI and the scheme of reducing leakage power consumption are presented, which are operated on the basis of IVC and transmission gate insertion scheme, and when the optimal input vector of sub-circuit is found, the leakage power consumption of the circuit is reduced on the non-critical path. At the same time, based on the NBTI effect of the mitigation circuit, the leakage power is further reduced on the critical path. Finally, the optimal input vector is obtained by combining the subcircuits to coordinate the NBTI effect and the leakage power loss of the mitigation circuit. Compared with IVC and gr cooperative optimization schemes, the proposed scheme can improve the rate of delay degradation by 0.51 times on the premise of almost the same leakage power consumption, which is more conducive to the mitigation of NBTI effect and the reduction of leakage power consumption.
【學位授予單位】：合肥工業(yè)大學
【學位級別】：碩士
【學位授予年份】：2017
【分類號】：TN402
本文編號：2137011
[Abstract]:As the process level of integrated circuits reaches the nanometer level, many negative effects of the devices gradually become apparent. The negative bias temperature instability (NBTI) effect is one of the most important factors affecting the reliability and service life of integrated circuits. The long term NBTI effect will lead to the increase of delay and the decrease of the speed of the circuit, and ultimately lead to the functional failure of the circuit. The analysis and research of NBTI effect has become one of the most important topics in the design of integrated circuits. At the same time, the reduction of voltage non-equal ratio brings a large leakage power (Leakage Power), which seriously affects the service life of the device. The research on how to reduce the leakage power is also one of the important contents in the field of low-power design. The current scheme uses input vector control (IVC) combined with gate substitution (gr) to mitigate the circuit aging caused by negative bias temperature instability (NBTI), but there is a problem that the application of gr may undermine the anti-aging effect of IVC. In this paper, a scheme combining input vector control and transmission gate (TG) insertion is proposed to mitigate the NBTI effect of the circuit. The optimal input control vector of the restored target circuit is obtained by inserting the transmission gate to eliminate the logic conflict caused by the merging sub-circuit. The experimental results show that the time delay degradation improvement rate of the proposed IVC and transmission gate scheme is 57.74 and the area overhead is 1.69. Compared with the IVC and gr scheme, the delay degradation improvement rate is 0.67 times higher and the area cost is reduced by 0.42 times. This scheme can better alleviate the NBTI aging effect of the circuit. The IVC and transmission gate insertion scheme in this paper only considers the mitigation of NBTI effect, but fails to reduce the static leakage power consumption of the circuit. In order to meet the low power requirement of integrated circuit design, the IVC and the transmission gate insert scheme only consider the mitigation of NBTI effect. In this paper, the cooperative mitigation circuit NBTI and the scheme of reducing leakage power consumption are presented, which are operated on the basis of IVC and transmission gate insertion scheme, and when the optimal input vector of sub-circuit is found, the leakage power consumption of the circuit is reduced on the non-critical path. At the same time, based on the NBTI effect of the mitigation circuit, the leakage power is further reduced on the critical path. Finally, the optimal input vector is obtained by combining the subcircuits to coordinate the NBTI effect and the leakage power loss of the mitigation circuit. Compared with IVC and gr cooperative optimization schemes, the proposed scheme can improve the rate of delay degradation by 0.51 times on the premise of almost the same leakage power consumption, which is more conducive to the mitigation of NBTI effect and the reduction of leakage power consumption.
【學位授予單位】：合肥工業(yè)大學
【學位級別】：碩士
【學位授予年份】：2017
【分類號】：TN402
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，本文編號：2137011
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