CMOS電荷泵鎖相環(huán)的分析與設(shè)計
發(fā)布時間：2018-07-20 12:14
【摘要】： 在研究大量資料的基礎(chǔ)之上,先對鎖相系統(tǒng)的基本工作原理進(jìn)行了分析,以傳統(tǒng)模擬鎖相環(huán)的結(jié)構(gòu)為基礎(chǔ),分析了鎖相環(huán)的數(shù)學(xué)模型,并以此為出發(fā)點對鎖相環(huán)的跟蹤性能、捕獲性能、及穩(wěn)定性等各種性能進(jìn)行了分析。由于本設(shè)計采用的是電荷泵鎖相環(huán)的形式,它的結(jié)構(gòu)與傳統(tǒng)的鎖相環(huán)有所不同,因此論文從系統(tǒng)設(shè)計角度出發(fā)對電荷泵鎖相環(huán)的工作原理、數(shù)學(xué)模型以及基本性能也進(jìn)行了比較詳細(xì)的分析,進(jìn)一步地研究了環(huán)路性能、環(huán)路參數(shù)。然后對電荷泵鎖相環(huán)的基本模塊——鑒頻鑒相器、電荷泵以及壓控振蕩器的常用電路進(jìn)行了結(jié)構(gòu)分析和性能比較。 本文設(shè)計了一個用于USB 2.0 PHY時鐘恢復(fù)電路的鎖相環(huán)頻率綜合器,論文主要闡述了這個電路系統(tǒng)的設(shè)計方法。環(huán)路中的鑒頻鑒相器采用了雙邊沿觸發(fā)的電路結(jié)構(gòu),有效地減小了傳統(tǒng)鑒頻鑒相器中的死區(qū)。電荷泵結(jié)構(gòu)也作了一定的改進(jìn),采用了消除過沖現(xiàn)象的電荷泵電路,減小了非理想因素。本文對鎖相環(huán)核心模塊壓控振蕩器進(jìn)行了深入研究與設(shè)計,實現(xiàn)了一個高線性度差分結(jié)構(gòu)的壓控振蕩器。分頻器采用單相時鐘TSPC邏輯實現(xiàn)。 電路設(shè)計和HSPICE仿真基于UMC0.25umCMOS工藝,從鎖相環(huán)的仿真結(jié)果可知,我們的理論研究結(jié)果和實驗結(jié)果相符。
[Abstract]:Based on the study of a large amount of data, the basic working principle of the phase-locked system is analyzed. Based on the structure of the traditional simulated PLL, the mathematical model of PLL is analyzed, and the tracking performance of PLL is taken as a starting point. The performance of capture and stability are analyzed. Because this design adopts the form of the charge pump phase-locked loop, its structure is different from the traditional phase-locked loop, so this paper starts from the system design angle to the charge pump phase-locked loop's working principle. The mathematical model and basic performance are also analyzed in detail, and the loop performance and loop parameters are further studied. Then, the structure analysis and performance comparison of the basic modules of the charge pump phase-locked loop frequency discriminator, charge pump and voltage-controlled oscillator are carried out. A phase-locked loop frequency synthesizer for USB 2.0 PHY clock recovery circuit is designed in this paper. The circuit structure of double edge trigger is adopted in the phase discriminator of the loop, which effectively reduces the dead zone in the traditional phase discriminator. The structure of the charge pump is improved to a certain extent, and the charge pump circuit is used to eliminate overshoot, which reduces the non-ideal factor. In this paper, the voltage controlled oscillator (VCO), which is the core module of PLL, is deeply studied and designed, and a VCO with high linearity difference structure is realized. The divider is implemented by single phase clock TSPC logic. The circuit design and HSPICE simulation are based on UMC 0.25 um CMOS process. From the simulation results of the PLL, we can see that our theoretical results are in agreement with the experimental results.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2007
【分類號】：TN911.8
本文編號：2133481
[Abstract]:Based on the study of a large amount of data, the basic working principle of the phase-locked system is analyzed. Based on the structure of the traditional simulated PLL, the mathematical model of PLL is analyzed, and the tracking performance of PLL is taken as a starting point. The performance of capture and stability are analyzed. Because this design adopts the form of the charge pump phase-locked loop, its structure is different from the traditional phase-locked loop, so this paper starts from the system design angle to the charge pump phase-locked loop's working principle. The mathematical model and basic performance are also analyzed in detail, and the loop performance and loop parameters are further studied. Then, the structure analysis and performance comparison of the basic modules of the charge pump phase-locked loop frequency discriminator, charge pump and voltage-controlled oscillator are carried out. A phase-locked loop frequency synthesizer for USB 2.0 PHY clock recovery circuit is designed in this paper. The circuit structure of double edge trigger is adopted in the phase discriminator of the loop, which effectively reduces the dead zone in the traditional phase discriminator. The structure of the charge pump is improved to a certain extent, and the charge pump circuit is used to eliminate overshoot, which reduces the non-ideal factor. In this paper, the voltage controlled oscillator (VCO), which is the core module of PLL, is deeply studied and designed, and a VCO with high linearity difference structure is realized. The divider is implemented by single phase clock TSPC logic. The circuit design and HSPICE simulation are based on UMC 0.25 um CMOS process. From the simulation results of the PLL, we can see that our theoretical results are in agreement with the experimental results.
【學(xué)位授予單位】：西安電子科技大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2007
【分類號】：TN911.8
【參考文獻(xiàn)】
相關(guān)期刊論文 前3條
1 王洪魁,袁小云,張瑞智;低噪聲、低功耗CMOS電荷泵鎖相環(huán)設(shè)計[J];固體電子學(xué)研究與進(jìn)展;2004年01期
2 魯昆生,王福昌;電荷泵鎖相環(huán)設(shè)計方法研究[J];華中理工大學(xué)學(xué)報;2000年01期
3 姜梅,劉三清,李乃平,陳釗;用于電荷泵鎖相環(huán)的無源濾波器的設(shè)計[J];微電子學(xué);2003年04期
，本文編號：2133481
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