【摘要】：隨著超大規(guī)模集成電路(VLSI)設(shè)計的快速發(fā)展,以及半導(dǎo)體工藝的不斷更新,使得芯片在性能上有了很大的提升,越來越多的智能移動設(shè)備、智能穿戴設(shè)備涌現(xiàn)于市場。芯片集成度的不斷提高,使其功耗和功耗密度問題也變得越來越突出。功耗的增加會引起芯片溫度提高,嚴(yán)重影響電路的可靠性,對于移動智能設(shè)備,功耗的增加會降低其續(xù)航能力。低功耗設(shè)計已經(jīng)成為VLSI設(shè)計的重要研究方向。一塊芯片全部的能耗中,時鐘網(wǎng)絡(luò)的功耗占據(jù)了總功耗的30%-50%,而觸發(fā)器是時鐘網(wǎng)絡(luò)電路中的主要部分,因此,低功耗觸發(fā)器的設(shè)計對降低電路整體功耗有重要意義。通過分析CMOS電路的功耗來源,以及觸發(fā)器的一些性能參數(shù),并實(shí)際舉例了典型的主從觸發(fā)器,介紹了關(guān)于觸發(fā)器的一些理論知識。在低功耗電路設(shè)計中,添加門控時鐘電路是常用的一種設(shè)計方法,門控時鐘技術(shù)的原理是利用使能信號控制電路在特定的時鐘周期內(nèi)讓其閑置,并使得電路在需要工作的時候被激活工作,門控時鐘技術(shù)的應(yīng)用減少了電路的整體功耗。本文基于門控時鐘電路設(shè)計了一種低功耗觸發(fā)器,可以較好地降低由于信號翻轉(zhuǎn)造成的動態(tài)功耗。在一定的時鐘周期內(nèi),如果輸入信號等于輸出信號,即輸入信號維持不變,那么門控時鐘信號可控制觸發(fā)器保持在閑置狀態(tài)。最后基于28nm工藝進(jìn)行了功能仿真,比較和分析了幾種觸發(fā)器的性能。分析可得,新設(shè)計的觸發(fā)器在降低功耗上有較好的效果。其次,利用了邏輯努力方法對現(xiàn)有的幾種主從觸發(fā)器,以及本文設(shè)計的低功耗雙門控觸發(fā)器進(jìn)行了優(yōu)化。邏輯努力方法不依賴于寄生參數(shù),使得電路設(shè)計在早期能通過簡單的計算得到其最小延遲,有可靠的評估。用邏輯努力方法優(yōu)化后的觸發(fā)器在理論上速度到達(dá)最優(yōu),設(shè)計者可根據(jù)其特點(diǎn)應(yīng)用在高速電路的關(guān)鍵路徑中。
[Abstract]:With the rapid development of VLSI design and the continuous updating of semiconductor technology, the performance of chips has been greatly improved. More and more smart mobile devices have emerged in the market. With the continuous improvement of chip integration, the problem of power consumption and power density becomes more and more prominent. The increase of power consumption will increase the temperature of the chip and seriously affect the reliability of the circuit. For mobile intelligent devices, the increase of power consumption will reduce its ability to live. Low power design has become an important research direction in VLSI design. Among the total energy consumption of a chip, the power consumption of the clock network occupies 30-50% of the total power consumption, while the trigger is the main part of the clock network circuit. Therefore, the design of the low-power flip-flop is of great significance to reduce the overall power consumption of the circuit. By analyzing the power sources of CMOS circuits and some performance parameters of flip-flops, a typical master-slave flip-flop is illustrated, and some theoretical knowledge about flip-flop is introduced. In the design of low power circuit, adding gated clock circuit is a common design method. The principle of gating clock technology is to make use of enable signal control circuit to idle it in a specific clock period. The circuit is activated when it needs to work, and the application of gating clock technology reduces the overall power consumption of the circuit. In this paper, a low power flip-flop based on gated clock circuit is designed, which can reduce the dynamic power consumption caused by signal flipping. In a certain clock cycle, if the input signal is equal to the output signal, that is, the input signal remains unchanged, then the gated clock signal can control the trigger to remain idle. Finally, the function simulation based on 28nm process is carried out, and the performance of several flip-flops is compared and analyzed. The analysis shows that the new flip-flop has a good effect on reducing power consumption. Secondly, several existing master-slave flip-flop and low-power double-gated flip-flop are optimized by using logical effort method. The logical effort method does not depend on parasitic parameters, so that the circuit design can get its minimum delay by simple calculation in the early stage and have reliable evaluation. The logic effort method is used to optimize the speed of the flip-flop in theory, and the designer can apply it to the critical path of high speed circuit according to its characteristics.
【學(xué)位授予單位】：安徽大學(xué)
【學(xué)位級別】：碩士
【學(xué)位授予年份】：2015
【分類號】：TN47;TN783

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本文編號：2128416