大功率射頻LDMOS器件設(shè)計(jì)優(yōu)化與建模
發(fā)布時(shí)間：2018-07-13 11:57
【摘要】：LDMOS(Lateral Double Diffused Metal Oxide Semiconductor)器件以其各方面的優(yōu)勢(shì)已經(jīng)基本取代雙極型器件成為射頻領(lǐng)域的主流技術(shù),由于RF LDMOS器件巨大的市場(chǎng)前景和重要的軍用價(jià)值,成為了半導(dǎo)體行業(yè)研究的熱點(diǎn),我國(guó)也已展開了對(duì)硅基RF LDMOS器件的研發(fā)工作。本設(shè)計(jì)的目標(biāo)是獲得一款大功率RF LDMOS器件,該器件采用雙層源極場(chǎng)板和背面源結(jié)構(gòu),利用半導(dǎo)體仿真軟件優(yōu)化設(shè)計(jì)器件結(jié)構(gòu)和各區(qū)域雜質(zhì)注入劑量,使器件具有較好的直流特性和頻率特性,然后根據(jù)器件具體結(jié)構(gòu)繪制器件版圖,并在上海華虹宏力半導(dǎo)體制造有限公司完成器件的制造。對(duì)小柵寬器件的直流測(cè)試結(jié)果表明,器件擊穿電壓大于100V,飽和電流密度大于180μA/μm,閾值電壓約為2.2V,對(duì)大柵寬封裝器件的測(cè)試結(jié)果表明,在頻率為1090MHz、漏源電壓為50V的測(cè)試條件下,器件最大輸出功率達(dá)到500W,效率達(dá)到45%,增益達(dá)到18dB,達(dá)到了設(shè)計(jì)指標(biāo)的要求。本論文還嘗試性地對(duì)器件進(jìn)行了小信號(hào)建模,提取了器件小信號(hào)等效電路中的寄生參數(shù)和本征參數(shù),并在ADS中進(jìn)行了優(yōu)化,基本完成了器件小信號(hào)模型的建立。探討了大信號(hào)建模的意義和基本思想,介紹了一種大信號(hào)建模方法。
[Abstract]:LDMOS (Lateral diffused Metal oxide Semiconductor) devices have basically replaced bipolar devices as the mainstream technology in RF field with its advantages in various aspects. Because of the huge market prospect and important military value of RF LDMOS devices, LDMOS devices have become a hot research topic in semiconductor industry. Research and development of silicon-based RF LDMOS devices have also been carried out in China. The purpose of this design is to obtain a high power RF LDMOS device. The device uses double-layer source polar field plate and backside source structure, and the semiconductor simulation software is used to optimize the design of device structure and impurity injection dose in each region. The device has better DC and frequency characteristics. Then the layout of the device is drawn according to the specific structure of the device, and the fabrication of the device is completed in Shanghai Huahong Hongli Semiconductor Manufacturing Co., Ltd. The DC test results of small gate width devices show that the breakdown voltage is more than 100 V, the saturation current density is more than 180 渭 A / 渭 m, and the threshold voltage is about 2.2 V. the test results for the large gate width packaging devices show that under the condition of 1090 MHz frequency and 50 V drain voltage, the breakdown voltage is more than 100 V, the saturation current density is more than 180 渭 A / 渭 m, and the threshold voltage is about 2.2 V. The maximum output power of the device is 500 W, the efficiency is 45 and the gain is 18 dB. The parasitic and intrinsic parameters of the small signal equivalent circuit are extracted and optimized in ads, and the small signal model of the device is established. The significance and basic idea of large signal modeling are discussed, and a large signal modeling method is introduced.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2016
【分類號(hào)】：TN386.1
本文編號(hào)：2119293
[Abstract]:LDMOS (Lateral diffused Metal oxide Semiconductor) devices have basically replaced bipolar devices as the mainstream technology in RF field with its advantages in various aspects. Because of the huge market prospect and important military value of RF LDMOS devices, LDMOS devices have become a hot research topic in semiconductor industry. Research and development of silicon-based RF LDMOS devices have also been carried out in China. The purpose of this design is to obtain a high power RF LDMOS device. The device uses double-layer source polar field plate and backside source structure, and the semiconductor simulation software is used to optimize the design of device structure and impurity injection dose in each region. The device has better DC and frequency characteristics. Then the layout of the device is drawn according to the specific structure of the device, and the fabrication of the device is completed in Shanghai Huahong Hongli Semiconductor Manufacturing Co., Ltd. The DC test results of small gate width devices show that the breakdown voltage is more than 100 V, the saturation current density is more than 180 渭 A / 渭 m, and the threshold voltage is about 2.2 V. the test results for the large gate width packaging devices show that under the condition of 1090 MHz frequency and 50 V drain voltage, the breakdown voltage is more than 100 V, the saturation current density is more than 180 渭 A / 渭 m, and the threshold voltage is about 2.2 V. The maximum output power of the device is 500 W, the efficiency is 45 and the gain is 18 dB. The parasitic and intrinsic parameters of the small signal equivalent circuit are extracted and optimized in ads, and the small signal model of the device is established. The significance and basic idea of large signal modeling are discussed, and a large signal modeling method is introduced.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2016
【分類號(hào)】：TN386.1
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