本文選題：FPGA + DDS��； 參考：《電子科技大學(xué)》2017年碩士論文

【摘要】：針對(duì)現(xiàn)有通用信號(hào)源功能不能滿足專用設(shè)備的測(cè)試需求,本文設(shè)計(jì)了一種基于FPGA和高速DAC技術(shù)相結(jié)合的多模多通道相參信號(hào)源的方法。該信號(hào)源充分利用低成本、高性能的FPGA邏輯資源豐富、速度快、可用管腳多、DDS IPCORE精度高以及可編程并行處理等特點(diǎn),產(chǎn)生多通道任意波形且相位可控的中射頻信號(hào),并通過(guò)高速DAC實(shí)現(xiàn)數(shù)模轉(zhuǎn)換。同時(shí),利用帶有第二奈奎斯特區(qū)輸出功能的高速DAC,如AD9119/AD9129,實(shí)現(xiàn)超奈奎斯特輸出,用于產(chǎn)生輸出頻率更高的更高的信號(hào)。本文的主要工作如下:介紹了FPGA產(chǎn)生多模式信號(hào)的設(shè)計(jì)結(jié)構(gòu)。為解決DAC轉(zhuǎn)換速率遠(yuǎn)高于現(xiàn)有FPGA器件的工作時(shí)鐘的問(wèn)題,詳細(xì)介紹了一種并行DDS信號(hào)產(chǎn)生方式。根據(jù)DAC的轉(zhuǎn)換速率,設(shè)計(jì)了并行信號(hào)產(chǎn)生過(guò)程中所需要的并行通道數(shù)量,然后基于FPGA的硬件資源與實(shí)現(xiàn)方法,詳細(xì)設(shè)計(jì)了各模式信號(hào)產(chǎn)生的結(jié)構(gòu),最后利用Verilog HDL語(yǔ)言對(duì)信號(hào)產(chǎn)生結(jié)構(gòu)進(jìn)行編程與仿真分析,用于驗(yàn)證編寫的Verilog HDL語(yǔ)言程序的正確性。介紹了多模多通道相參信號(hào)源的硬件設(shè)計(jì)平臺(tái)。根據(jù)多模多通道相參信號(hào)源的技術(shù)指標(biāo)要求,詳細(xì)介紹了一種基于FPGA、高速DAC、兩級(jí)同步相位校正的硬件電路的設(shè)計(jì)方案,并詳細(xì)介紹了兩級(jí)多通道相位同步的設(shè)計(jì)方法與實(shí)現(xiàn)方式。并根據(jù)DAC的特性參數(shù)以及奈奎斯特第一區(qū)、第二區(qū)及第三區(qū)的輸出頻率響應(yīng)特性,通過(guò)切換DAC工作時(shí)鐘,擴(kuò)展了輸出信號(hào)頻率范圍,避免了輸出信號(hào)頻率在0.5倍采樣率、1倍采樣率及1.5倍采樣率附近時(shí),輸出功率較小的現(xiàn)象。測(cè)試了多模多通道相參信號(hào)源的輸出。根據(jù)多模信號(hào)的數(shù)學(xué)原理及仿真分析結(jié)果、多模信號(hào)的產(chǎn)生方法,在硬件平臺(tái)上分別測(cè)試了多模信號(hào)的輸出頻譜,以及多通道同步信號(hào)的輸出時(shí)域波形,測(cè)試結(jié)果與理論分析一致,從而驗(yàn)證了設(shè)計(jì)方法的可行性與正確性。綜上所述,本文設(shè)計(jì)的基于FPGA和高速DAC技術(shù)相結(jié)合的多模多通道相參信號(hào)源具有一定的可行性與使用價(jià)值。
[Abstract]:In view of the fact that the existing universal signal source function can not meet the test requirements of special equipment, this paper designs a method of multi-mode multi-channel coherent signal source based on FPGA and high-speed DAC technology. This signal source makes full use of the advantages of low cost, high performance FPGA logic resources, high speed, high precision of multi-pin DDS IPCORE and programmable parallel processing, so it can produce multi-channel arbitrary waveform and controllable phase middle frequency signal. Digital to analog conversion is realized by high speed DAC. At the same time, using the high speed DAC with the output function of the second Nyquist region, such as AD9119 / AD9129, the ultra-Nyquist output is realized, which is used to generate higher frequency signals. The main work of this paper is as follows: the design structure of multi-mode signal generated by FPGA is introduced. In order to solve the problem that DAC conversion rate is much higher than the working clock of existing FPGA devices, a parallel DDS signal generation method is introduced in detail. According to the conversion rate of DAC, the number of parallel channels needed in the process of parallel signal generation is designed. Then, based on the hardware resources and implementation method of FPGA, the structure of each mode signal generation is designed in detail. Finally, the signal generation structure is programmed and simulated with Verilog HDL, which is used to verify the correctness of the program written in Verilog HDL. The hardware design platform of multi-mode multi-channel coherent signal source is introduced. According to the technical requirements of multi-mode and multi-channel coherent signal source, a hardware circuit based on FPGA, high speed DAC and two-stage synchronous phase correction is introduced in detail. The design and implementation of two-stage multi-channel phase synchronization are introduced in detail. According to the characteristic parameters of DAC and the output frequency response characteristics of the first, second and third regions of Nyquist, the output frequency range is extended by switching the clock of DAC. It avoids the phenomenon that the output power is smaller when the output signal frequency is near the sampling rate of one or five times the sampling rate of 0.5 times and the sampling rate of 1.5 times. The output of multi-mode multi-channel coherent signal source is tested. According to the mathematical principle of multi-mode signal and the result of simulation analysis, the output spectrum of multi-mode signal and the output time-domain waveform of multi-channel synchronous signal are tested on the hardware platform. The test results are consistent with the theoretical analysis, which verifies the feasibility and correctness of the design method. To sum up, the multi-mode multi-channel coherent signal source based on FPGA and high-speed DAC technology is feasible and valuable.
【學(xué)位授予單位】：電子科技大學(xué)
【學(xué)位級(jí)別】：碩士
【學(xué)位授予年份】：2017
【分類號(hào)】：TN791

【參考文獻(xiàn)】

相關(guān)期刊論文 前10條

1 劉鑫;任勇峰;儲(chǔ)成群;方煒;鄭永秋;;相位可控多通道任意波形信號(hào)源卡設(shè)計(jì)[J];儀表技術(shù)與傳感器;2015年03期

2 楊韜儀;王超;夏艷琴;;基于并行DDS技術(shù)的寬帶通信信號(hào)模擬方法[J];微電子學(xué);2014年06期

3 曾志輝;張一鳴;陶海軍;朱學(xué)政;;新型相位差可調(diào)的多通道信號(hào)發(fā)生器設(shè)計(jì)[J];科學(xué)技術(shù)與工程;2014年17期

4 沙芬芬;張祥坤;;基于FPGA波形存儲(chǔ)法合成大寬帶DDS信號(hào)源設(shè)計(jì)與實(shí)現(xiàn)[J];測(cè)試技術(shù)學(xué)報(bào);2013年04期

5 宋征;許國(guó)宏;李星;;基于AD9959的高精度多通道雷達(dá)信號(hào)源設(shè)計(jì)[J];電子設(shè)計(jì)工程;2012年17期

6 侯鈺龍;盧一男;張會(huì)新;;并行多通道模擬信號(hào)發(fā)生器的設(shè)計(jì)與實(shí)現(xiàn)[J];電視技術(shù);2012年17期

7 彭波;吳學(xué)杰;;基于AD9959的多通道信號(hào)源設(shè)計(jì)[J];工業(yè)控制計(jì)算機(jī);2012年08期

8 趙彬廣;高文軍;李坤龍;馬小兵;;基于數(shù)字相關(guān)法的多通道DAC同步算法[J];中國(guó)科學(xué)院研究生院學(xué)報(bào);2012年02期

9 胡茂海;蔣鴻宇;嚴(yán)俊;文豪;富艷琴;;基于AD9910的多通道信號(hào)發(fā)生器[J];信息與電子工程;2012年01期

10 曹鄭蛟;滕召勝;李華忠;張倩;溫和;;基于FPGA的DDS信號(hào)發(fā)生器設(shè)計(jì)[J];計(jì)算機(jī)測(cè)量與控制;2011年12期

相關(guān)碩士學(xué)位論文 前10條

1 項(xiàng)云龍;多通道寬帶信號(hào)發(fā)生器的設(shè)計(jì)和實(shí)現(xiàn)[D];國(guó)防科學(xué)技術(shù)大學(xué);2013年

2 張雷;多通道脈沖信號(hào)發(fā)生器的設(shè)計(jì)[D];哈爾濱工業(yè)大學(xué);2012年

3 張凱琳;基于FPGA和DDS多路信號(hào)源的設(shè)計(jì)與實(shí)現(xiàn)[D];中北大學(xué);2012年

4 周艮;基于FPGA的多模式信號(hào)源的研制[D];武漢理工大學(xué);2012年

5 汪東雷;基于FPGA的多模式信號(hào)源的研究與實(shí)現(xiàn)[D];國(guó)防科學(xué)技術(shù)大學(xué);2010年

6 孫素平;基于DDS技術(shù)信號(hào)發(fā)生器的研究與設(shè)計(jì)[D];哈爾濱工業(yè)大學(xué);2010年

7 張?zhí)m英;雙通道寬帶信號(hào)發(fā)生器的設(shè)計(jì)[D];哈爾濱理工大學(xué);2010年

8 王晨;基于DDS的信號(hào)產(chǎn)生技術(shù)研究[D];西安電子科技大學(xué);2010年

9 金杰;基于DDS的相控陣天線信號(hào)發(fā)生器的設(shè)計(jì)與實(shí)現(xiàn)[D];南京航空航天大學(xué);2010年

10 趙永輝;多通道參量陣信號(hào)源及功放電路設(shè)計(jì)[D];哈爾濱工程大學(xué);2010年

，

本文編號(hào)：2110830